JPS6476775A - Manufacture of junction type field-effect transistor - Google Patents

Manufacture of junction type field-effect transistor

Info

Publication number
JPS6476775A
JPS6476775A JP23231287A JP23231287A JPS6476775A JP S6476775 A JPS6476775 A JP S6476775A JP 23231287 A JP23231287 A JP 23231287A JP 23231287 A JP23231287 A JP 23231287A JP S6476775 A JPS6476775 A JP S6476775A
Authority
JP
Japan
Prior art keywords
thickness
type
epitaxial layer
region
channel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP23231287A
Other languages
Japanese (ja)
Other versions
JPH0682687B2 (en
Inventor
Masanori Yamamoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP23231287A priority Critical patent/JPH0682687B2/en
Publication of JPS6476775A publication Critical patent/JPS6476775A/en
Publication of JPH0682687B2 publication Critical patent/JPH0682687B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Landscapes

  • Junction Field-Effect Transistors (AREA)

Abstract

PURPOSE:To thinly form a second semiconductor layer and a gate impurity region, and improve the cotrollability of channel thickness, by forming a first semiconductor layer and a second semiconductor layer of inverse conductivity type wherein a part is eliminated, on a conductivity type semiconductor substrate, and selectively introducing a conductivity type impurity into the eliminated part to form a gate impurity region. CONSTITUTION:A first N-type epitaxial layer 2 is subjected to etching, by using a thermal oxide film 3 to a mask, and a P-type semiconductor substrate 1 is exposed. On the whole surface, a second N-type epitaxial layer 5 is formed in thickness of 1-2mum. By using a mask such as oxide film and photo resist, P-type impurity in the recessed part of the second N-type epitaxial layer 5 is selectively introduced to form a P-type impurity region 6 in thickness of 0.5-1mum. In the second epitaxial layer 5 between the region 6 and the substrate 1, a channel is formed by the impurity region 6. The thickness tepi to determine the channel thickness (d), and the thickness tp of the region 6 can be made less than or equal to one-half of prior ones. Therefore, the channel thickness (d) can be very precisely formed, and the controllability of drain.source current is improved.
JP23231287A 1987-09-18 1987-09-18 Method for manufacturing junction field effect transistor Expired - Lifetime JPH0682687B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23231287A JPH0682687B2 (en) 1987-09-18 1987-09-18 Method for manufacturing junction field effect transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23231287A JPH0682687B2 (en) 1987-09-18 1987-09-18 Method for manufacturing junction field effect transistor

Publications (2)

Publication Number Publication Date
JPS6476775A true JPS6476775A (en) 1989-03-22
JPH0682687B2 JPH0682687B2 (en) 1994-10-19

Family

ID=16937230

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23231287A Expired - Lifetime JPH0682687B2 (en) 1987-09-18 1987-09-18 Method for manufacturing junction field effect transistor

Country Status (1)

Country Link
JP (1) JPH0682687B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5101241A (en) * 1989-11-20 1992-03-31 Kabushiki Kaisha Toshiba Telescopic paper guide means movable to selected receiving trays
EP3477706A1 (en) * 2017-10-30 2019-05-01 Analog Devices Global Unlimited Company Low gate current junction field effect transistor

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5101241A (en) * 1989-11-20 1992-03-31 Kabushiki Kaisha Toshiba Telescopic paper guide means movable to selected receiving trays
EP3477706A1 (en) * 2017-10-30 2019-05-01 Analog Devices Global Unlimited Company Low gate current junction field effect transistor
CN109728100A (en) * 2017-10-30 2019-05-07 亚德诺半导体无限责任公司 Low grid current junction field effect transistor device architectures

Also Published As

Publication number Publication date
JPH0682687B2 (en) 1994-10-19

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