JPS6476363A - Memory for two-dimensional data - Google Patents

Memory for two-dimensional data

Info

Publication number
JPS6476363A
JPS6476363A JP23512487A JP23512487A JPS6476363A JP S6476363 A JPS6476363 A JP S6476363A JP 23512487 A JP23512487 A JP 23512487A JP 23512487 A JP23512487 A JP 23512487A JP S6476363 A JPS6476363 A JP S6476363A
Authority
JP
Japan
Prior art keywords
access
units
address
circuits
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP23512487A
Other languages
Japanese (ja)
Inventor
Takashi Hamada
Hiroshi Nishikawa
Yoshihiro Hayakawa
Katsura Kawakami
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP23512487A priority Critical patent/JPS6476363A/en
Publication of JPS6476363A publication Critical patent/JPS6476363A/en
Pending legal-status Critical Current

Links

Landscapes

  • Image Input (AREA)

Abstract

PURPOSE:To realize the high-speed input/output of 2-dimensional data by adding a shape correction circuit to each memory unit together with a correction circuit which converts a picture element address into an address to be applied to each memory unit so that the 2-dimensional access is possible to the peripheral picture elements of a noticed one simultaneously with access given to the noticed picture element. CONSTITUTION:The memory units 109-112 which can work simultaneously with each other are provided. Then the address correction circuits 101-104 which function to secure 1:1 correspondence between each data within an area at an optional position consisting of the same number of data and each memory unit are added to the units 109-112 together with the shape correction circuits 105-108 respectively. The circuits 101-104 produce the addresses to the units 109-112 and the circuits 105-108 correct the difference in shape between a desired access area and a rectangular area to each address. These corrected addresses are used to access the units 109-112. Thus the simultaneous access is possible to the data stored in the desired areas set at optional positions.
JP23512487A 1987-09-18 1987-09-18 Memory for two-dimensional data Pending JPS6476363A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23512487A JPS6476363A (en) 1987-09-18 1987-09-18 Memory for two-dimensional data

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23512487A JPS6476363A (en) 1987-09-18 1987-09-18 Memory for two-dimensional data

Publications (1)

Publication Number Publication Date
JPS6476363A true JPS6476363A (en) 1989-03-22

Family

ID=16981408

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23512487A Pending JPS6476363A (en) 1987-09-18 1987-09-18 Memory for two-dimensional data

Country Status (1)

Country Link
JP (1) JPS6476363A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5462343A (en) * 1993-11-18 1995-10-31 Toyota Jidosha Kabushiki Kaisha Hydraulic pressure booster having booster piston and valve mechanism associated with mechanically operated and electrically controlled pressure regulators

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5462343A (en) * 1993-11-18 1995-10-31 Toyota Jidosha Kabushiki Kaisha Hydraulic pressure booster having booster piston and valve mechanism associated with mechanically operated and electrically controlled pressure regulators

Similar Documents

Publication Publication Date Title
DE3689209D1 (en) Direct input and output in a virtual memory arrangement.
DE3485329D1 (en) ELECTRONIC CASH REGISTER.
DE68912277D1 (en) Output buffer circuit.
DE69128434D1 (en) Bit stack compatible input / output circuit
DE3361916D1 (en) Series/parallel/series shift register memory comprising redundant parallel-connected storage registers, and display apparatus comprising a picture memory thus organized
KR900014989A (en) A partial write control circuit used in a memory unit.
JPS6476363A (en) Memory for two-dimensional data
JPS6482275A (en) Digital image processor
DE69100796D1 (en) Integrated memory circuit with redundancy and improved addressing in test mode.
DE68926541D1 (en) Address modification circuit
DE68915284D1 (en) CIRCUIT TESTING.
TW329952U (en) Multiple input/output devices having shared address space
BR8006769A (en) MEMORY OF SERIES-PARALELOSERIE CCD WITH FAN OUTPUT AND FAN INPUT CIRCUITS
DK451085A (en) COMMON ADDRESS REGISTERS FOR MAIN STORAGE AND PLATE CONTROL UNIT STORES
SE8304934L (en) POWER DISTRIBUTOR DEVICE
ES491634A0 (en) IMAGE MEMORY ADDRESSING PROCEDURE AND IMPROVEMENTS IN THE CORRESPONDING SYSTEMS
WO1996008767A3 (en) Microcontroller system with a multiple-register stacking instruction
JPS52149924A (en) Address converter
JPS6488733A (en) Tablet input device
JPS55166747A (en) Data processor
JPS54116846A (en) Picture processing memory unit
KR900005443U (en) Output port assignment circuit that can be accessed on the same address
KR890003933U (en) Memory peripheral circuit for PIP (Picture in Picture)
JPS55126869A (en) Scan conversion system
TW247976B (en) Circuit for matrix multiplication