JPS647388Y2 - - Google Patents
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- Publication number
- JPS647388Y2 JPS647388Y2 JP11205983U JP11205983U JPS647388Y2 JP S647388 Y2 JPS647388 Y2 JP S647388Y2 JP 11205983 U JP11205983 U JP 11205983U JP 11205983 U JP11205983 U JP 11205983U JP S647388 Y2 JPS647388 Y2 JP S647388Y2
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- power supply
- output
- power
- level
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000003990 capacitor Substances 0.000 claims description 25
- 238000001514 detection method Methods 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 6
- 239000004020 conductor Substances 0.000 description 3
- 230000005669 field effect Effects 0.000 description 2
Description
【考案の詳細な説明】
本考案は、集積回路内のフリツプフロツプなど
の記憶要素の状態を電源投入時にセツト又はリセ
ツトして一定の状態にするパワーオンクリア回路
に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a power-on clear circuit that sets or resets the state of a storage element such as a flip-flop in an integrated circuit to a constant state when power is turned on.
集積回路には各種ゲート、フリツプフロツプな
どの回路要素が搭載されており、そのうちフリツ
プフロツプなど複数個の状態のうちの1つを安定
的にとる素子は電源投入時つまり動作開始時には
セツト状態からその状態を、またリセツト状態な
らそのリセツト状態を確実にとることが望まれる
場合が多い。かゝる初期状態設定は外部からセツ
ト又はリセツト信号を入力することによつても可
能であるが、この場合は当然集積回路のピン数が
1つ増えてしまう。そこで内部に、電源投入で該
信号を発生する回路を設けることが考えられてい
る。 Integrated circuits are equipped with circuit elements such as various gates and flip-flops. Among these, elements such as flip-flops that stably take one of several states change from the set state when the power is turned on, that is, when operation begins. In addition, in the case of a reset state, it is often desired to securely maintain the reset state. Such initial state setting can also be performed by inputting a set or reset signal from the outside, but in this case, the number of pins of the integrated circuit naturally increases by one. Therefore, it has been considered to provide an internal circuit that generates the signal when the power is turned on.
かゝるパワーオンクリア回路の従来例を第1図
および第3図に示す。第1図の回路はpチヤンネ
ル電界効果トランジスタQ1,Q2と抵抗Rとnチ
ヤンネル電界効果トランジスタQ3からなり、電
源投入で電源電圧VDDが第2図の曲線VDDで示す
ように上昇開始すると、抵抗RによりVDDに吊ら
れている端子P1は第2図曲線P1で示すように浮
遊容量を充電しながら該VDDと連動して上昇して
いく。VDDが例えば1Vのスレツシヨルド電圧Vth
(ここではQ1〜Q3のVthはすべて同じとする)に
達するとトランジスタQ1はオンとなり、端子P2
の電位は第2図の曲線P2に示すように上昇を始
める。この端子P2の電位がVthに達するとnチヤ
ンネルトランジスタQ3はオンとなり(こゝでは
VSS=0とする)、端子P1の電位は図示の如く下
降する。こうして山形の電圧が端子P1に得られ、
これはインバータI1,I22段で整形したのちフリ
ツプフロツプ等に対するクリア信号Scとなる。こ
の回路は抵抗Rによる点P1の電位上昇と、トラ
ンジスタQ1,Q3による該点P1の電位引下げ各動
作の時間差を利用し、その時間差の間クリア信号
を発生するものであるから、電源電圧VDDの上昇
が比較的緩やかであると充分な時間差が得られ、
所望パルス幅のクリア信号が得られる。これに反
してVDDの立上りが急峻であると該時間差は小に
なり、クリアパルスは極めて細幅となつて確実な
動作が保証できない。またこの回路では電源オン
状態ではトランジスタQ1〜Q3のすべてがオンで
あり、Q1,Q2およびR,Q3を通る電流が常に消
費される。CMOSは休止状態では電流を流さな
いという利点があるが、このパワーオンクリア回
路ではそうでなく、定常電流を流してしまう。 Conventional examples of such power-on clear circuits are shown in FIGS. 1 and 3. The circuit shown in Fig. 1 consists of p-channel field effect transistors Q 1 and Q 2 , a resistor R, and an n-channel field effect transistor Q 3. When the power is turned on, the power supply voltage V DD rises as shown by the curve V DD in Fig. 2. When starting, the terminal P1 , which is suspended to VDD by the resistor R, increases in conjunction with the VDD while charging the stray capacitance, as shown by the curve P1 in FIG. Threshold voltage V th where V DD is e.g. 1V
(Here, it is assumed that all V th of Q 1 to Q 3 are the same), transistor Q 1 turns on, and terminal P 2
The potential of begins to rise as shown by curve P 2 in Figure 2. When the potential of this terminal P2 reaches Vth , the n-channel transistor Q3 turns on (in this case,
(V SS =0), the potential of terminal P 1 falls as shown. A chevron voltage is thus obtained at terminal P 1 ,
After this is shaped by two stages of inverters I 1 and I 2 , it becomes a clear signal S c for flip-flops and the like. This circuit utilizes the time difference between raising the potential at point P1 by resistor R and lowering the potential at point P1 by transistors Q1 and Q3 , and generates a clear signal during that time difference. If the power supply voltage V DD rises relatively slowly, a sufficient time difference can be obtained.
A clear signal with the desired pulse width is obtained. On the other hand, if the rise of V DD is steep, the time difference becomes small and the clear pulse becomes extremely narrow, making it impossible to guarantee reliable operation. Further, in this circuit, all transistors Q 1 to Q 3 are on when the power is on, and current passing through Q 1 , Q 2 and R, Q 3 is constantly consumed. CMOS has the advantage of not passing any current when it is in rest mode, but this is not the case with this power-on-clear circuit, and instead a steady current flows.
第3図の回路は、容量で回路状態の初期設定を
行なおうとするものである。I3〜I6はインバー
タ、S1〜S4はnチヤンネルFETとpチヤンネル
FETを並列に接続し各ゲートへはクロツクCKと
その反転信号を加えるようにしたスイツチで
図示接続から明らかなようにS1,S3とS2,S4は互
いに逆の開閉を行なう。これはラツチ回路を構成
し、S2,S4がオンのときI3,I5の入力がHレベル
ならI4,I6の入力はLレベル従つてその出力はH
レベルとなり、これがI3,I5の入力に入つてラツ
チされ、以後入力がなくてもこの状態を保つ。
C1〜C4は初期設定を行うコンデンサで、C1は第
1段インバータI3の出力端を電源VDDへC2は段2
段インバータI4の出力端を電源(グランド)VSS
へ、C3は第3段インバータI5の出力端を電源VDD
へ、C4は第4段インバータI6の出力端を電源VSS
へ接続する。つまりこれらのコンデンサは縦続接
続された各インバータの出力端P3,P4,P5,P6
(これは次段インバータの入力端でもある)を交
互に電源VDDまたはVSSへ接続する。電源投入時
を考えるとコンデンサC1,C3は点P3,P5をHレ
ベルに引上げ、コンデンサC2,C4は点P4,P6を
Lレベルへ引下げ、従つてマスター側ラツチI3と
I4、スレーブ側ラツチI5とI6はかゝるH,L状態
を定常的にとることになる。こうして初期設定が
行なわれる。 The circuit shown in FIG. 3 attempts to initialize the circuit state using capacitance. I3 to I6 are inverters, S1 to S4 are n-channel FET and p-channel
FETs are connected in parallel, and a switch is configured to apply a clock CK and its inverted signal to each gate, and as is clear from the illustrated connections, S 1 , S 3 and S 2 , S 4 open and close in opposite directions. This constitutes a latch circuit, and when S 2 and S 4 are on, if the inputs of I 3 and I 5 are at H level, the inputs of I 4 and I 6 are at L level, so their outputs are at H level.
level, which enters the inputs of I 3 and I 5 and is latched, maintaining this state even if there is no input thereafter.
C1 to C4 are capacitors that perform initial settings, and C1 connects the output end of the first stage inverter I3 to the power supply VDD.C2 connects the output end of the first stage inverter I3 to the power supply VDD .
Connect the output end of stage inverter I 4 to the power supply (ground) V SS
, C 3 connects the output end of the third stage inverter I 5 to the power supply V DD
to, C 4 connects the output end of the fourth stage inverter I 6 to the power supply V SS
Connect to. In other words, these capacitors are connected to the output terminals P 3 , P 4 , P 5 , P 6 of each cascaded inverter.
(this is also the input terminal of the next stage inverter) are connected alternately to the power supply V DD or V SS . Considering when the power is turned on, capacitors C 1 and C 3 pull up points P 3 and P 5 to H level, capacitors C 2 and C 4 pull down points P 4 and P 6 to L level, and therefore master side latch I 3 and
I 4 and the slave side latches I 5 and I 6 are constantly in the H and L states. Initial settings are performed in this way.
しかしこの回路では、クロツクCK,発生回
路も集積回路内に搭載され、電源オンで動作状態
となるが、その時の出力状態がH,Lいずれかは
不定である。もしCKがHレベル、従つてがL
レベルであるとデータ取込み用のスイツチS1は
開、ラツチ用スイツチS2は閉となり、点P3,P4
がコンデンサによりH,Lに設定されても入力端
子に入るデータDiによりこれが反転されてしまう
恐れがある。つまり回路では電源オン時にクロツ
クがラツチモードであつて呉れゝば問題はないが
上述の様にデータ取込みモードになるとフリツプ
フロツプI3〜I6の状態はデータDiによつて定まり、
予定状態にはならない。 However, in this circuit, the clock CK and generation circuit are also mounted in the integrated circuit, and the circuit becomes operational when the power is turned on, but whether the output state is H or L at that time is uncertain. If CK is H level, therefore L
level, the data acquisition switch S 1 is open, the latch switch S 2 is closed, and the points P 3 and P 4
Even if D i is set to H or L by the capacitor, there is a risk that this will be inverted by the data D i entering the input terminal. In other words, in the circuit, there is no problem if the clock is in latch mode when the power is turned on, but as mentioned above, when it enters data acquisition mode, the states of flip-flops I 3 to I 6 are determined by data D i ,
It will not be in the planned state.
なおこの第3図の回路でのクリアは信号により
行なうのではなく、コンデンサC1〜C4により行
なう。これらのコンデンサは回路動作時にその動
作速度を遅くするという欠点はあるが、リセツト
信号をもらうことなく自身で初期設定を行なつて
おり、しかもコンデンサは電極配線の浮遊容量利
用で形成でき、クリア信号を必要とするもののよ
うにクリア信号配線を引かなければならないとい
う必要がなく、簡単であるという特徴がある。 Note that clearing in the circuit of FIG. 3 is not performed by a signal, but by capacitors C 1 to C 4 . Although these capacitors have the disadvantage of slowing down the operating speed of the circuit, they do the initial setting by themselves without receiving a reset signal, and the capacitors can be formed by using the stray capacitance of the electrode wiring, so they do not require a clear signal. Unlike those that require clear signal wiring, there is no need to draw clear signal wiring, and the feature is that it is simple.
いずれにしても従来のパワーオンリセツト回路
は動作が不確実であるという欠点がある。本考案
はかゝる点を改善しようとするもので、その特徴
は論理反転機能を有する2つの論理ゲート回路を
交叉接続してなり、該2つの論理ゲート回路のう
ちの一方の論理ゲート回路の出力端はコンデンサ
により電源の高電位側へ、他方の論理ゲート回路
の出力端は他のコンデンサにより電源の低電位側
へ接続し、該一方の論理ゲート回路は該他方の論
理ゲート回路よりスレツシヨルド電圧を高くした
フリツプフロツプと、該フリツプフロツプの出力
によりクリアされる回路群の各回路と該フリツプ
フロツプのリセツト端子との間に接続され、各回
路が全てクリアされた時にリセツト信号を出力す
る論理回路とを有し、上記回路群のクリア検出出
力は各々コンデンサを介して電源の高電位側へ接
続した点にある。以下実施例を参照しながらこれ
を詳細に説明する。 In any case, conventional power-on reset circuits have the disadvantage of unreliable operation. The present invention attempts to improve this point, and its feature is that two logic gate circuits having a logic inversion function are cross-connected, and one of the two logic gate circuits is The output terminal is connected to the high potential side of the power supply by a capacitor, and the output terminal of the other logic gate circuit is connected to the low potential side of the power supply by another capacitor, and one logic gate circuit has a threshold voltage higher than the other logic gate circuit. A logic circuit is connected between each circuit of a circuit group that is cleared by the output of the flip-flop and the reset terminal of the flip-flop, and outputs a reset signal when all the circuits are cleared. However, the clear detection outputs of the above circuit group are each connected to the high potential side of the power supply via a capacitor. This will be explained in detail below with reference to Examples.
第4図は本考案に係る回路の基本部分を示し、
I7,I8はインバータであつて入,出力端をクロス
接続されてフリツプフロツプを構成する。C5は
インバータI7の出力端と電源VDD間に接続したコ
ンデンサ、C6はインバータI8の出力端と電源VSS
間に接続したコンデンサである。これらの出力端
およびその配線には必らず浮遊容量が付くが、図
面ではそれをC7,C8で示す。このような構成で
あると電源オン時にはインバータI7の出力端従つ
てインバータI8の入力端はコンデンサC5により電
源VDDへ吊り上げられて(C5>C7であるからC7に
よるVSSへの引下げ力は弱い)Hレベルになりイ
ンバータI8の出力端従つてインバータI7の入力端
はコンデンサC6により電源VSSへ引張られて(C6
>C8である)Lレベルになる。一旦このような
状態になると、これは相互にラツチして不変とな
る。第5図はこれを説明する図で曲線P7,P8は
第4図の節点P7,P8の電位変化を示す。電源VDD
が通常の速度以上で上昇する場合は以上の通りで
あるが、電源立上りが極めてゆつくりしたもので
あるとコンデンサC5,C6の引上げ、引下げ作用
は充分に利かないことが予想できる。このような
場合にも対処すべく本考案ではインバータI7,I8
のスレツシヨルドレベルを異ならせる。第6図の
曲線I7はインバータI7の、また曲線I8はインバー
タI8の入力電圧Vi対出力電圧V0特性であり、イン
バータI7は3V以上をHレベル、インバータI8は
2V以上をHレベルと判断する例を示す。このよ
うにしておくと、点P7,P8が同じ電位をとる最
悪事態になつたとしても電源電圧VDDが2.5Vまで
上昇するときインバータI7はLレベル、インバー
タI8はHレベルと感じ、それぞれH,L出力状態
となる。こうして電源が遅く立上つてもまた急速
に立上つてもインバータI7の出力がH、インバー
タI8の出力がLの予定のレベルをとらせることが
できる。この出力端P7の電位はクリヤ信号Scとな
るが、このまゝでは該信号Scは電源VDDと共に立
上り、電源オン状態では常にHレベルの信号とな
る。これをLレベルにして電源投入時にのみオン
になるクリア信号を得るには該フリツプフロツプ
をリセツトすればよい。第7図にその回路を示
す。 Figure 4 shows the basic part of the circuit according to the present invention,
I 7 and I 8 are inverters whose input and output terminals are cross-connected to form a flip-flop. C 5 is a capacitor connected between the output terminal of inverter I 7 and power supply V DD , and C 6 is the capacitor connected between the output terminal of inverter I 8 and power supply V SS
This is the capacitor connected between the two. These output terminals and their wiring necessarily have stray capacitance, which is indicated by C 7 and C 8 in the drawing. With this configuration, when the power is turned on, the output terminal of inverter I 7 and the input terminal of inverter I 8 are pulled up to the power supply V DD by capacitor C 5 (since C 5 > C 7 , V SS due to C 7 The pulling force to V SS becomes H level ( the pulling force to
> C 8 ) becomes L level. Once in this state, they latch together and remain unchanged. FIG. 5 is a diagram for explaining this, and curves P 7 and P 8 show potential changes at nodes P 7 and P 8 in FIG. 4. Power supply VDD
The above is the case when C rises at a speed higher than the normal speed, but if the power supply rises extremely slowly, it can be predicted that the pulling up and pulling actions of capacitors C 5 and C 6 will not be sufficiently effective. In order to cope with such cases, the present invention uses inverters I 7 and I 8
have different threshold levels. Curve I 7 in Figure 6 is the input voltage V i vs. output voltage V 0 characteristic of inverter I 7 , and curve I 8 is the input voltage V i vs. output voltage V 0 characteristic of inverter I 8 .
An example of determining 2V or more as H level is shown below. By doing this, even in the worst case where points P 7 and P 8 have the same potential, when the power supply voltage V DD rises to 2.5V, inverter I 7 will go to L level and inverter I 8 will go to H level. The output state is H and L, respectively. In this way, even if the power supply starts up slowly or quickly, the output of the inverter I7 can be at the H level and the output of the inverter I8 can be at the L level. The potential of this output terminal P7 becomes a clear signal S c , but if left as is, this signal S c rises together with the power supply V DD , and is always an H level signal when the power is on. To obtain a clear signal that is set to L level and turns on only when the power is turned on, the flip-flop can be reset. FIG. 7 shows the circuit.
第7図でI7,C5,C6は第4図と同じ回路で、唯
リセツト信号を入れるためインバータI8はナンド
ゲートNGに変えており、またコンデンサC7,C8
は図示を省略している。CGはパワーオンクリア
されるべきフリツプフロツプ等を含む集積回路チ
ツプ上の回路群である。NORはノアゲートで、
この複数の入力端へは回路群CG内の各素子のク
リアされたことを示す信号例えばフリツプフロツ
プのQ出力Sg1〜Sgoが導かれる。 In Fig. 7, I 7 , C 5 , and C 6 are the same circuits as in Fig. 4, except that the inverter I 8 has been changed to a NAND gate NG in order to input the reset signal, and the capacitors C 7 and C 8
are omitted from illustration. CG is a group of circuits on an integrated circuit chip, including flip-flops, etc., that are to be cleared on power-on. NOR is Noah Gate,
Signals indicating that each element in the circuit group CG has been cleared, for example, Q outputs S g1 -S go of flip-flops, are led to the plurality of input terminals.
この回路では電源オン時に上述のようにして確
実にクリア信号Scが発生し、回路群CGをクリア
する。クリアされると信号Sg1……SgoはすべてL
レベルになり、ノアゲートNORの出力はHレベ
ル、インバータI9の出力はLレベルになり、ナン
ドゲートNGの出力はHレベルになる。これはイ
ンバータI7の出力従つてクリア信号ScをLレベル
にする。こうして本回路によればパワーオン時に
確実にクリア信号が発生し、かつ回路群がクリア
されたとき該クリア信号が消滅し、極めて確実な
パワーオンクリアが行なわれる。なおC9,C10,
C11〜C1oは電源オン時にインバータI9の出力導
体、入力導体および信号Sg1〜Sgoの導線をH,L
レベルにする、C5,C6と同様なコンデンサであ
る。特にコンデンサC11〜C1oは回路群CGのリセ
ツトを確実に検出する機能を持つ。即ちまだリセ
ツトパルスを受けないのに信号Sg1〜Sgoの線のあ
るもの、場合によつてはすべてがLレベルになつ
ていることがあり得るが、特に後者の場合はノア
ゲートNORの出力がH、インバータI9の出力が
LになつてクリアパルスScが直ちにLレベルされ
又は最初から出力しない場合もあり得る。コンデ
ンサC11〜C1oでこれらの信号線を電源VDDへ吊つ
ておけば、かゝるエラーは確実に防止できる。 In this circuit, when the power is turned on, the clear signal S c is reliably generated as described above, and the circuit group CG is cleared. When cleared, signal S g1 ...S go is all L
The output of the NAND gate NOR becomes H level, the output of inverter I9 becomes L level, and the output of NAND gate NG becomes H level. This causes the output of the inverter I7 and hence the clear signal Sc to go to L level. In this way, according to the present circuit, a clear signal is reliably generated when the power is turned on, and the clear signal disappears when the circuit group is cleared, so that an extremely reliable power-on clear is performed. Note that C 9 , C 10 ,
C 11 to C 1o connect the output conductor, input conductor, and signal S g1 to S go conductors of inverter I 9 to H and L when the power is turned on.
It is a capacitor similar to C 5 and C 6 that sets the level. In particular, capacitors C 11 to C 1o have a function of reliably detecting the reset of circuit group CG. In other words, even though the reset pulse has not yet been received, some of the signal lines S g1 to S go may be at L level, and in some cases, all of them may be at L level. Especially in the latter case, the output of the NOR gate NOR is H, the output of the inverter I9 becomes L and the clear pulse S c may be immediately set to the L level or may not be output from the beginning. If these signal lines are connected to the power supply V DD using capacitors C 11 to C 1o , such errors can be reliably prevented.
以上詳細に説明したように本考案によれば、電
源の立上り特性、入力データなどに依存しない、
極めて確実なパワーオンクリアを行なうことがで
き、高信頼度を要求される集積回路に用いて効果
がある。 As explained in detail above, according to the present invention, the
It is possible to perform extremely reliable power-on clear, and is effective for use in integrated circuits that require high reliability.
第1図〜第3図は従来のパワーオンクリア回路
の回路図および動作説明用波形図、第4図は本考
案回路の基本部分の回路図、第5図および第6図
はその動作説明用波形図、第7図は本考案の実施
例を示す回路図である。
図面でI7,NGはインバータ、VDDは電源の高電
位側、VSSは電源の低電位側、C5,C6はコンデン
サ、NOR,I9はリセツト信号出力回路である。
Figures 1 to 3 are circuit diagrams and waveform diagrams for explaining the operation of a conventional power-on clear circuit, Figure 4 is a circuit diagram of the basic part of the circuit of the present invention, and Figures 5 and 6 are for explaining its operation. The waveform diagram and FIG. 7 are circuit diagrams showing an embodiment of the present invention. In the drawing, I 7 and NG are inverters, V DD is the high potential side of the power supply, V SS is the low potential side of the power supply, C 5 and C 6 are capacitors, and NOR and I 9 are reset signal output circuits.
Claims (1)
交叉接続してなり、該2つの論理ゲート回路のう
ちの一方の論理ゲート回路の出力端はコンデンサ
により電源の高電位側へ、他方の論理ゲート回路
の出力端は他のコンデンサにより電源の低電位側
へ接続し、該一方の論理ゲート回路は該他方の論
理ゲート回路よりスレツシヨルド電圧を高くした
フリツプフロツプと、該フリツプフロツプの出力
によりクリアされる回路群の各回路と該フリツプ
フロツプのリセツト端子との間に接続され、各回
路が全てクリアされた時にリセツト信号を出力す
る論理回路とを有し、上記回路群のクリア検出出
力は各々コンデンサを介して電源の高電位側へ接
続したことを特徴とするパワーオンクリア回路。 The output terminal of one of the two logic gate circuits is connected to the high potential side of the power supply by a capacitor, and the output terminal of the other logic gate circuit is connected to the high potential side of the power supply by a capacitor. The output end is connected to the low potential side of the power supply by another capacitor, and one logic gate circuit has a flip-flop whose threshold voltage is higher than that of the other logic gate circuit, and each of a group of circuits that are cleared by the output of the flip-flop. The logic circuit is connected between the circuit and the reset terminal of the flip-flop and outputs a reset signal when all the circuits are cleared, and the clear detection output of the circuit group is connected to the high voltage of the power supply via a capacitor. A power-on clear circuit characterized by being connected to the potential side.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11205983U JPS5949239U (en) | 1983-07-19 | 1983-07-19 | Power-on clear circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11205983U JPS5949239U (en) | 1983-07-19 | 1983-07-19 | Power-on clear circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5949239U JPS5949239U (en) | 1984-04-02 |
JPS647388Y2 true JPS647388Y2 (en) | 1989-02-28 |
Family
ID=30259920
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP11205983U Granted JPS5949239U (en) | 1983-07-19 | 1983-07-19 | Power-on clear circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5949239U (en) |
-
1983
- 1983-07-19 JP JP11205983U patent/JPS5949239U/en active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS5949239U (en) | 1984-04-02 |
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