JPS6473422A - System controller - Google Patents

System controller

Info

Publication number
JPS6473422A
JPS6473422A JP62230673A JP23067387A JPS6473422A JP S6473422 A JPS6473422 A JP S6473422A JP 62230673 A JP62230673 A JP 62230673A JP 23067387 A JP23067387 A JP 23067387A JP S6473422 A JPS6473422 A JP S6473422A
Authority
JP
Japan
Prior art keywords
low speed
clock
controls
program
controlled
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62230673A
Other languages
Japanese (ja)
Inventor
Kimio Yamamura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Hudson Soft Co Ltd
Original Assignee
Seiko Epson Corp
Hudson Soft Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp, Hudson Soft Co Ltd filed Critical Seiko Epson Corp
Priority to JP62230673A priority Critical patent/JPS6473422A/en
Publication of JPS6473422A publication Critical patent/JPS6473422A/en
Priority to US08/137,213 priority patent/US5483659A/en
Pending legal-status Critical Current

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  • Executing Machine-Instructions (AREA)

Abstract

PURPOSE:To control the system of high speed operation, and to eliminate the need for a complicated interface circuit by switching the clock of the system according to a program, and in addition, starting up the system from a low speed mode when power is applied. CONSTITUTION:A control means 1 decodes the program, stored in a storing means 5, and determines the speed of the system clock. It controls a system clock generating means so as to generate the system clock corresponding to said speed. At the same time, it controls so as to start up the system from the low speed mode when the power is applied. Thus, the peripheral circuit of a low speed operation can be controlled without necessitating the complicated interface circuit, and in addition, the system for a television game, etc., to operate at high speed can be controlled as well.
JP62230673A 1987-09-14 1987-09-14 System controller Pending JPS6473422A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP62230673A JPS6473422A (en) 1987-09-14 1987-09-14 System controller
US08/137,213 US5483659A (en) 1987-09-14 1993-10-18 Apparatus for controlling a signal processing system to operate in high and low speed modes

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62230673A JPS6473422A (en) 1987-09-14 1987-09-14 System controller

Publications (1)

Publication Number Publication Date
JPS6473422A true JPS6473422A (en) 1989-03-17

Family

ID=16911507

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62230673A Pending JPS6473422A (en) 1987-09-14 1987-09-14 System controller

Country Status (1)

Country Link
JP (1) JPS6473422A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02307112A (en) * 1989-02-28 1990-12-20 Internatl Business Mach Corp <Ibm> Clock signal generator

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54117649A (en) * 1978-03-06 1979-09-12 Fujitsu Ltd Speed variable-type central processing unit
JPS5870335A (en) * 1981-10-21 1983-04-26 Hitachi Ltd Switching system of synchronizing clock

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54117649A (en) * 1978-03-06 1979-09-12 Fujitsu Ltd Speed variable-type central processing unit
JPS5870335A (en) * 1981-10-21 1983-04-26 Hitachi Ltd Switching system of synchronizing clock

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02307112A (en) * 1989-02-28 1990-12-20 Internatl Business Mach Corp <Ibm> Clock signal generator

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