JPS6468664A - Peak holding circuit - Google Patents

Peak holding circuit

Info

Publication number
JPS6468664A
JPS6468664A JP22559287A JP22559287A JPS6468664A JP S6468664 A JPS6468664 A JP S6468664A JP 22559287 A JP22559287 A JP 22559287A JP 22559287 A JP22559287 A JP 22559287A JP S6468664 A JPS6468664 A JP S6468664A
Authority
JP
Japan
Prior art keywords
current
signal
amplifier
capacitor
peak
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP22559287A
Other languages
Japanese (ja)
Inventor
Toru Kanno
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ricoh Research Institute of General Electronics Co Ltd
Ricoh Co Ltd
Original Assignee
Ricoh Research Institute of General Electronics Co Ltd
Ricoh Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ricoh Research Institute of General Electronics Co Ltd, Ricoh Co Ltd filed Critical Ricoh Research Institute of General Electronics Co Ltd
Priority to JP22559287A priority Critical patent/JPS6468664A/en
Publication of JPS6468664A publication Critical patent/JPS6468664A/en
Pending legal-status Critical Current

Links

Landscapes

  • Measurement Of Current Or Voltage (AREA)

Abstract

PURPOSE:To accurately detect the peak of a fast signal for a long time by rectifying a signal obtained by amplifying the difference between an input and an output signal and outputting the signal generated by integrating its current. CONSTITUTION:A differential amplifier A1 which amplifies a voltage in current form amplifies the difference between the input signal ein and output signal eout. Its output current i1 flows to current type rectifies D1 and D2 and only a current i2 flowing to the D2 flows to the inverted input terminal of an amplifier A2 and a capacitor Dc. The amplifier A2 and capacitor Cc operate as an integration circuit for the i2 and outputs eout proportional to the integral value of the current i2. In this constitution, A1 is a current source with high impedance, so the impedance when the D2 is on exerts a little influence upon frequency characteristics (tracking characteristics). For the purpose, the capacitor Cc is made small and the amplification factor of the amplifier A1 is increased to detect the peak of the fast signal for a long time.
JP22559287A 1987-09-08 1987-09-08 Peak holding circuit Pending JPS6468664A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP22559287A JPS6468664A (en) 1987-09-08 1987-09-08 Peak holding circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22559287A JPS6468664A (en) 1987-09-08 1987-09-08 Peak holding circuit

Publications (1)

Publication Number Publication Date
JPS6468664A true JPS6468664A (en) 1989-03-14

Family

ID=16831735

Family Applications (1)

Application Number Title Priority Date Filing Date
JP22559287A Pending JPS6468664A (en) 1987-09-08 1987-09-08 Peak holding circuit

Country Status (1)

Country Link
JP (1) JPS6468664A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2428097A (en) * 2005-07-07 2007-01-17 Agilent Technologies Inc Error signal averaging circuit
JP2011009938A (en) * 2009-06-24 2011-01-13 Toyota Central R&D Labs Inc Hold circuit
JP2012227674A (en) * 2011-04-19 2012-11-15 Mitsubishi Electric Corp Hold circuit
JP2013501408A (en) * 2009-07-29 2013-01-10 クゥアルコム・インコーポレイテッド Switch with variable control voltage
US10211830B2 (en) 2017-04-28 2019-02-19 Qualcomm Incorporated Shunt termination path

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2428097A (en) * 2005-07-07 2007-01-17 Agilent Technologies Inc Error signal averaging circuit
US7710186B2 (en) 2005-07-07 2010-05-04 Avago Technologies General Ip (Singapore) Pte. Ltd. Averaging circuit apparatus, error signal generation system and method of averaging an error signal
JP2011009938A (en) * 2009-06-24 2011-01-13 Toyota Central R&D Labs Inc Hold circuit
JP2013501408A (en) * 2009-07-29 2013-01-10 クゥアルコム・インコーポレイテッド Switch with variable control voltage
JP2012227674A (en) * 2011-04-19 2012-11-15 Mitsubishi Electric Corp Hold circuit
US10211830B2 (en) 2017-04-28 2019-02-19 Qualcomm Incorporated Shunt termination path

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