JPS6466578A - Delay analysis system of logical circuit - Google Patents
Delay analysis system of logical circuitInfo
- Publication number
- JPS6466578A JPS6466578A JP22456987A JP22456987A JPS6466578A JP S6466578 A JPS6466578 A JP S6466578A JP 22456987 A JP22456987 A JP 22456987A JP 22456987 A JP22456987 A JP 22456987A JP S6466578 A JPS6466578 A JP S6466578A
- Authority
- JP
- Japan
- Prior art keywords
- path
- logical circuit
- circuit model
- delay time
- control
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000003213 activating effect Effects 0.000 abstract 2
Landscapes
- Management, Administration, Business Operations System, And Electronic Commerce (AREA)
- Tests Of Electronic Circuits (AREA)
Abstract
PURPOSE:To easily judge the quality of a delay analytical result, by judging whether a path exceeding a delay time is the meaningless redundant path on a logical circuit according to a route activating method and removing the redundant path from a delay analytical result list. CONSTITUTION:A logical circuit model load means 2 reads a logical circuit model from a logical circuit model file 1 to load a logical circuit model table 3 and a control is transferred to a path detecting/ delay time calculating means 4. The means 4 takes out the path between the start and final points of the logical circuit model of the table 3 and calculates a delay time to store the same in a detected path memory means 7 and, when the path of the logical circuit model of the table 3 is not entirely detected at that point of time, control is transferred to a control value comparing means 6. The means 6 compares the delay time stored in the means 7 with a limit value 5 and, when said delay time is a contravention path, control is transferred to a redundant path judge means 9. The means 9 judges whether the contravention path is a redundant path an effective path using a route activating method; when said path is the effective path (error path), an error path display means 8 is started to output said path as error path display 10.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP22456987A JPS6466578A (en) | 1987-09-08 | 1987-09-08 | Delay analysis system of logical circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP22456987A JPS6466578A (en) | 1987-09-08 | 1987-09-08 | Delay analysis system of logical circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6466578A true JPS6466578A (en) | 1989-03-13 |
Family
ID=16815818
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP22456987A Pending JPS6466578A (en) | 1987-09-08 | 1987-09-08 | Delay analysis system of logical circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6466578A (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH03184460A (en) * | 1989-12-14 | 1991-08-12 | Anritsu Corp | Charge collection type cordless telephone set |
JPH03231174A (en) * | 1990-02-07 | 1991-10-15 | Fujitsu Ltd | Test pattern generator |
JPH0587422A (en) * | 1991-09-27 | 1993-04-06 | Showa Alum Corp | Cooling panel with frost-preventive coat for evaporator |
US6317861B1 (en) | 1995-04-20 | 2001-11-13 | Nec Corporation | Delay verification device for logic circuit and delay verification method therefor |
US7093216B2 (en) * | 2003-02-06 | 2006-08-15 | Kabushiki Kaisha Toshiba | Apparatus connectable to a computer network for circuit design verification, computer implemented method for circuit design verification, and computer program product for controlling a computer system so as to verify circuit designs |
-
1987
- 1987-09-08 JP JP22456987A patent/JPS6466578A/en active Pending
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH03184460A (en) * | 1989-12-14 | 1991-08-12 | Anritsu Corp | Charge collection type cordless telephone set |
JPH03231174A (en) * | 1990-02-07 | 1991-10-15 | Fujitsu Ltd | Test pattern generator |
JPH0587422A (en) * | 1991-09-27 | 1993-04-06 | Showa Alum Corp | Cooling panel with frost-preventive coat for evaporator |
US6317861B1 (en) | 1995-04-20 | 2001-11-13 | Nec Corporation | Delay verification device for logic circuit and delay verification method therefor |
US7093216B2 (en) * | 2003-02-06 | 2006-08-15 | Kabushiki Kaisha Toshiba | Apparatus connectable to a computer network for circuit design verification, computer implemented method for circuit design verification, and computer program product for controlling a computer system so as to verify circuit designs |
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