JPS6465860A - Socket for semiconductor package - Google Patents
Socket for semiconductor packageInfo
- Publication number
- JPS6465860A JPS6465860A JP62223373A JP22337387A JPS6465860A JP S6465860 A JPS6465860 A JP S6465860A JP 62223373 A JP62223373 A JP 62223373A JP 22337387 A JP22337387 A JP 22337387A JP S6465860 A JPS6465860 A JP S6465860A
- Authority
- JP
- Japan
- Prior art keywords
- cover
- semiconductor package
- steps
- package
- base
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Testing Of Individual Semiconductor Devices (AREA)
- Tests Of Electronic Circuits (AREA)
- Connecting Device With Holders (AREA)
Abstract
PURPOSE:To improve an EB tester in resolusion and enable a failure analysis of a semiconductor package by a method wherein an opening is provided to a part of a cover which corresponds to the position of a semiconductor chip built inside a semiconductor package and a clamper is made to clamp the cover at the position lower than the semiconductor package. CONSTITUTION:A recessed part 4 where a semiconductor package 10 is fitted is provided to the upper face of a base 1 and a upper end 5a of a contact pin 5 is extracted and protrudes from the rear of the recessed part 4. Both ends of the base 1 are made to be steps 6 lower than the part where the recessed part 4 is provided. A cover 2 is formed into such a shape that its both ends are made to be steps 7 lower than its center part as well as the base 1 and it is hat-shaped in a side view, and the steps 6 are made to be jointed with the steps 7 when the package 10 is pressed down by clamping through the clamper 3. The center part of the cover 2 is bored to provide a window 8, so that the inside of the package 10 can be observed through the window 8. By these processes, an objective lens 20 of a EB tester can be improved in resolution by making it approach the cover and a failure analysis can be easily performed as well.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62223373A JPS6465860A (en) | 1987-09-07 | 1987-09-07 | Socket for semiconductor package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62223373A JPS6465860A (en) | 1987-09-07 | 1987-09-07 | Socket for semiconductor package |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6465860A true JPS6465860A (en) | 1989-03-13 |
Family
ID=16797127
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62223373A Pending JPS6465860A (en) | 1987-09-07 | 1987-09-07 | Socket for semiconductor package |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6465860A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5691041A (en) * | 1995-09-29 | 1997-11-25 | International Business Machines Corporation | Socket for semi-permanently connecting a solder ball grid array device using a dendrite interposer |
| US6521479B1 (en) * | 2001-12-28 | 2003-02-18 | Texas Instruments Incorporated | Repackaging semiconductor IC devices for failure analysis |
| WO2011033768A1 (en) * | 2009-09-15 | 2011-03-24 | パナソニック株式会社 | Signal observation apparatus and signal observation method |
| US7924022B2 (en) | 2007-03-19 | 2011-04-12 | Fujitsu Limited | Evaluation board and failure location detection method |
-
1987
- 1987-09-07 JP JP62223373A patent/JPS6465860A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5691041A (en) * | 1995-09-29 | 1997-11-25 | International Business Machines Corporation | Socket for semi-permanently connecting a solder ball grid array device using a dendrite interposer |
| US6521479B1 (en) * | 2001-12-28 | 2003-02-18 | Texas Instruments Incorporated | Repackaging semiconductor IC devices for failure analysis |
| US7924022B2 (en) | 2007-03-19 | 2011-04-12 | Fujitsu Limited | Evaluation board and failure location detection method |
| WO2011033768A1 (en) * | 2009-09-15 | 2011-03-24 | パナソニック株式会社 | Signal observation apparatus and signal observation method |
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