JPS6459827A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS6459827A
JPS6459827A JP62216857A JP21685787A JPS6459827A JP S6459827 A JPS6459827 A JP S6459827A JP 62216857 A JP62216857 A JP 62216857A JP 21685787 A JP21685787 A JP 21685787A JP S6459827 A JPS6459827 A JP S6459827A
Authority
JP
Japan
Prior art keywords
lsi chip
wiring board
substrate
insulating film
protruding electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62216857A
Other languages
Japanese (ja)
Inventor
Hiroaki Fujimoto
Kenzo Hatada
Takao Ochi
Hideji Tamura
Kazufumi Ogawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP62216857A priority Critical patent/JPS6459827A/en
Publication of JPS6459827A publication Critical patent/JPS6459827A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body

Landscapes

  • Wire Bonding (AREA)

Abstract

PURPOSE:To enhance a close contact force between an insulating resin and an LSI chip and a wiring board and to enhance reliability of moistureproofness and thermal resistance by a method wherein an insulating film chemically bonded to a substrate is installed on the surface of the LSI chip and the surface of the wiring board. CONSTITUTION:An insulating resin 4 is coated on a face having a conductor wiring part 2 of a wiring board 1 composed of glass or the like and having an insulating film 3 chemically bonded to a substrate. A protruding electrode 6 of an LSI chip 5 having the protruding electrode 6 and having an insulating film 7 chemically bonded to a substrate is aligned with the conductor wiring part 2; the LSI chip 5 is pressed to the wiring board 1 by using a pressurization tool 8. The LSI chip 5 is bonded firmly by the insulating resin 4; the protruding electrode 6 is connected electrically to the conductor wiring part 2 by contact due to a contractile force caused by hardening.
JP62216857A 1987-08-31 1987-08-31 Semiconductor device Pending JPS6459827A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62216857A JPS6459827A (en) 1987-08-31 1987-08-31 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62216857A JPS6459827A (en) 1987-08-31 1987-08-31 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS6459827A true JPS6459827A (en) 1989-03-07

Family

ID=16694995

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62216857A Pending JPS6459827A (en) 1987-08-31 1987-08-31 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS6459827A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7170145B2 (en) 2003-04-28 2007-01-30 Sharp Kabushiki Kaisha Method of manufacturing semiconductor device, flexible substrate, and semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7170145B2 (en) 2003-04-28 2007-01-30 Sharp Kabushiki Kaisha Method of manufacturing semiconductor device, flexible substrate, and semiconductor device

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