JPS6457654A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS6457654A
JPS6457654A JP21315187A JP21315187A JPS6457654A JP S6457654 A JPS6457654 A JP S6457654A JP 21315187 A JP21315187 A JP 21315187A JP 21315187 A JP21315187 A JP 21315187A JP S6457654 A JPS6457654 A JP S6457654A
Authority
JP
Japan
Prior art keywords
type
high concentration
mos transistor
transistor
wells
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP21315187A
Other languages
Japanese (ja)
Inventor
Keiichiro Shimizu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP21315187A priority Critical patent/JPS6457654A/en
Publication of JPS6457654A publication Critical patent/JPS6457654A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H01L27/0623—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with bipolar transistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To reduce sufficiently the current amplification factor of a parasitic transistor, by forming an N-type or P-type high concentration semiconductor region having diffusion depth deeper than the wells of an N-type and a P-type MOS transistors, in the boundary part between the forming region of the N-type MOS transistor and that of the P-type MOS transistor. CONSTITUTION:In a semiconductor device of Bi-CMOS structure in which a bipolar transistor and a CMOS transistor are formed at the same time, an N-type or P-type high concentration semiconductor region 6 having diffusion depth deeper than the wells 4, 5 of an N-type transistor and P-type transistors is formed, in the boundary part between the forming region of the N-type MOS transistor and that of the P-type MOS transistor. For example, after an N-type high concentration buried layer 2 and a P-type high concentration buries layer 3 are formed in a P-type silicon substrate 1, N-type epitaxial growth is performed, and the P-well or both of the P and N-wells are diffused to form the P-type substrate 4 of an N-type MOS transistor and the N-type substrate 5 of an P-MOS transistor. Then the N-type high concentration semiconductor region 6 is formed reaching the N-type high concentration buried layer 2.
JP21315187A 1987-08-28 1987-08-28 Semiconductor device Pending JPS6457654A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21315187A JPS6457654A (en) 1987-08-28 1987-08-28 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21315187A JPS6457654A (en) 1987-08-28 1987-08-28 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS6457654A true JPS6457654A (en) 1989-03-03

Family

ID=16634414

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21315187A Pending JPS6457654A (en) 1987-08-28 1987-08-28 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS6457654A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5091760A (en) * 1989-04-14 1992-02-25 Kabushiki Kaisha Toshiba Semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5091760A (en) * 1989-04-14 1992-02-25 Kabushiki Kaisha Toshiba Semiconductor device
US5340751A (en) * 1989-04-14 1994-08-23 Kabushiki Kaisha Toshiba Method of manufacturing a BiMOS device

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