JPS6457644U - - Google Patents

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Publication number
JPS6457644U
JPS6457644U JP15259387U JP15259387U JPS6457644U JP S6457644 U JPS6457644 U JP S6457644U JP 15259387 U JP15259387 U JP 15259387U JP 15259387 U JP15259387 U JP 15259387U JP S6457644 U JPS6457644 U JP S6457644U
Authority
JP
Japan
Prior art keywords
contact pin
power supply
holes
pins
power
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15259387U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP15259387U priority Critical patent/JPS6457644U/ja
Publication of JPS6457644U publication Critical patent/JPS6457644U/ja
Pending legal-status Critical Current

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  • Tests Of Electronic Circuits (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Measuring Leads Or Probes (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案の一実施例を示すLSI試験機
の構成図、第2図は従来のLSI試験機の構成例
を示した図、第3図は他のプローブカードの例を
示した図、である。 図において、3a〜3dは探針、3a′〜3d
′はスルーホール、4a〜4dは取り付け具、7
はテスタヘツド、8は電源供給ピン、9a〜9d
は信号入出力ピン、10,10′は基準孔、11
,11′はガイドピン、12はテーブル、21は
プローブカード、22はプリント基板、22a〜
22dは導体、23は導体、23′はスルーホー
ル、23a′〜23d′はスルーホール、24a
〜24dはパツド、25は電源用パツド、25′
はスルーホール、26は電源リング基板、26a
′〜26d′,26a″〜26d″は貫通孔、2
7は電源用コンタクトピン、28はコンタクトピ
ン、31はウエハ、32はLSIチツプ、32a
〜32dはボンデイングパツド、をそれぞれ表わ
す。
Fig. 1 is a diagram showing the configuration of an LSI testing machine that is an embodiment of the present invention, Fig. 2 is a diagram showing an example of the configuration of a conventional LSI testing machine, and Fig. 3 is a diagram showing an example of another probe card. , is. In the figure, 3a to 3d are probes, 3a' to 3d
' is a through hole, 4a to 4d are attachments, 7
is the tester head, 8 is the power supply pin, 9a to 9d
are signal input/output pins, 10, 10' are reference holes, 11
, 11' is a guide pin, 12 is a table, 21 is a probe card, 22 is a printed circuit board, 22a~
22d is a conductor, 23 is a conductor, 23' is a through hole, 23a' to 23d' are through holes, 24a
~24d is pad, 25 is power pad, 25'
is a through hole, 26 is a power ring board, 26a
'~26d', 26a''~26d'' are through holes, 2
7 is a power supply contact pin, 28 is a contact pin, 31 is a wafer, 32 is an LSI chip, 32a
-32d represent bonding pads, respectively.

Claims (1)

【実用新案登録請求の範囲】 テーブル上に載置したLSIチツプに設けてあ
る複数のボンデイングパツトにプローブカードの
下面に備えた複数の探針を圧接すると共に、該プ
ローブカード上面に設けてある複数のパツドにテ
スタヘツドの信号入出力ピンと電源供給ピンとを
圧接して前記LSIチツプを試験する試験機にお
いて、 上記プローブカードが電源リング基板26とプ
リント基板22との組合せによつて構成されてお
り、 該電源リング基板26には該基板に一体化固定
してある電源用コンタクトピン27と、 着脱自在な複数個のコンタクトピン28および
該コンタクトピン28用の複数組の貫通孔26a
′と26a″〜26d′と26d″と、 を備え、 またプリント基板22には、 電源用コンタクトピン27の一端が挿入される
スルーホール25′を備えた電源用パツド25と
、 電源用コンタクトピン27の他端が挿入される
スルーホール23′とコンタクトピン28の一端
が挿入される複数のスルーホール23a′〜23
d′を備えた導体23と、 コンタククトピン28の他端が挿入される複数
のスルーホール3a′〜3d′を備えた複数のパ
ツド24a〜24dと、 を上面に、 また下面には複数の探針3a〜3dを備えて構
成されることを特徴とするLSI試験機。
[Claims for Utility Model Registration] A plurality of probes provided on the bottom surface of a probe card are pressed against a plurality of bonding pads provided on an LSI chip placed on a table. In the testing machine for testing the LSI chip by pressing the signal input/output pins and power supply pins of the tester head onto the pads of the tester, the probe card is constituted by a combination of a power ring board 26 and a printed circuit board 22, and The power ring board 26 includes a power contact pin 27 that is integrally fixed to the board, a plurality of removable contact pins 28, and a plurality of sets of through holes 26a for the contact pins 28.
', 26a'' to 26d' and 26d'', and the printed circuit board 22 includes a power supply pad 25 having a through hole 25' into which one end of a power supply contact pin 27 is inserted, and a power supply contact pin. A through hole 23' into which the other end of the contact pin 27 is inserted and a plurality of through holes 23a' to 23 into which one end of the contact pin 28 is inserted.
d', and a plurality of pads 24a to 24d each having a plurality of through holes 3a' to 3d' into which the other end of the contact pin 28 is inserted. An LSI testing machine comprising probes 3a to 3d.
JP15259387U 1987-10-05 1987-10-05 Pending JPS6457644U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15259387U JPS6457644U (en) 1987-10-05 1987-10-05

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15259387U JPS6457644U (en) 1987-10-05 1987-10-05

Publications (1)

Publication Number Publication Date
JPS6457644U true JPS6457644U (en) 1989-04-10

Family

ID=31427661

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15259387U Pending JPS6457644U (en) 1987-10-05 1987-10-05

Country Status (1)

Country Link
JP (1) JPS6457644U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008300481A (en) * 2007-05-30 2008-12-11 Micronics Japan Co Ltd Semiconductor inspection apparatus

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008300481A (en) * 2007-05-30 2008-12-11 Micronics Japan Co Ltd Semiconductor inspection apparatus

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