JPS6455797A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To facilitate the high integration of a high speed memory element by being equipped with first and second transistors to select respectively input data with a word signal and an erasing signal, a memory transistor and a capacity for reading, writing and transferring the data. CONSTITUTION:Between a bit line BL and a clock signal line phiP, a memory cell selecting transistor T1, an FLOTOX type memory transistor M1 for a non- volatile storage, an erasing mode selecting transistor T2 and an MOS capacitor C1 to execute the storing at the time of a RAM action are serially connected. The MOS capacitor C1 executes the function to raise a node N1 to a high voltage with a clock signal phiP, and for this reason, the tunnel area of the memory transistor M1 is provided at the transistor T2 side. Thus, a non-volatile RAM is usually operated at a high speed as the RAM, the data of the RAM are stored into a non-volatile memory as needed, the non-volatile of the storage data after the power source is lost is assured and the high integration can be facilitated.