JPS6454822A - Digital agc circuit - Google Patents
Digital agc circuitInfo
- Publication number
- JPS6454822A JPS6454822A JP21185087A JP21185087A JPS6454822A JP S6454822 A JPS6454822 A JP S6454822A JP 21185087 A JP21185087 A JP 21185087A JP 21185087 A JP21185087 A JP 21185087A JP S6454822 A JPS6454822 A JP S6454822A
- Authority
- JP
- Japan
- Prior art keywords
- value
- shifted
- multiplication
- agc
- coarse adjustment
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Dc Digital Transmission (AREA)
- Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
- Control Of Amplification And Gain Control (AREA)
Abstract
PURPOSE:To compress the hardware of a variable gain generating means and a multiplication means, by providing a coarse adjustment AGC circuit by a shift means in an automatic gain control AGC circuit. CONSTITUTION:The average value of prescribed number of digital values outputted from a digital AGC just before is shifted 4 so that the same leading '0' of the value can be set as the leading '0' of a targeted value, and coarse adjustment AGC is performed by using the number of shift in which the above shifted number and the shifted number used in a previous coarse adjustment AGC are added 11. As for a fine adjustment coefficient, a ratio of an averaged level value shifted 3 to the same leading '0' to the targeted value of the average level is calculated 5, and the fine adjustment gain at a previous time and the gain of multiplication 7 can be obtained, therefore, a small value can be obtained, and an area for multiplication is stabilized by decided accuracy. In such a way, it is possible to reduce the output bit length of the variable gain generating means 5 and the input bit length of the multiplication means 6, thereby, to compress the hardware of a multiplier.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP21185087A JPS6454822A (en) | 1987-08-25 | 1987-08-25 | Digital agc circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP21185087A JPS6454822A (en) | 1987-08-25 | 1987-08-25 | Digital agc circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6454822A true JPS6454822A (en) | 1989-03-02 |
JPH0531328B2 JPH0531328B2 (en) | 1993-05-12 |
Family
ID=16612626
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP21185087A Granted JPS6454822A (en) | 1987-08-25 | 1987-08-25 | Digital agc circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6454822A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5996389A (en) * | 1996-09-07 | 1999-12-07 | Eht Werkzeugmaschinen Gmbh | Machining center for processing flat workpieces with a segment distributed hold-down |
JP5382393B1 (en) * | 2013-02-15 | 2014-01-08 | 東洋システム株式会社 | Digital AGC control method and feedback control apparatus |
-
1987
- 1987-08-25 JP JP21185087A patent/JPS6454822A/en active Granted
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5996389A (en) * | 1996-09-07 | 1999-12-07 | Eht Werkzeugmaschinen Gmbh | Machining center for processing flat workpieces with a segment distributed hold-down |
JP5382393B1 (en) * | 2013-02-15 | 2014-01-08 | 東洋システム株式会社 | Digital AGC control method and feedback control apparatus |
WO2014125753A1 (en) * | 2013-02-15 | 2014-08-21 | 東洋システム株式会社 | Digital agc control method and feedback control device |
US9391573B2 (en) | 2013-02-15 | 2016-07-12 | Toyo System Co., Ltd. | Digital AGC control method and feedback control apparatus |
Also Published As
Publication number | Publication date |
---|---|
JPH0531328B2 (en) | 1993-05-12 |
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