JPS6454755A - Memory - Google Patents

Abstract

PURPOSE:To reduce the area of a cell by forming the lower electrode of the capacity of adjacent memories having a switching transistor and a laminated capacity of a first conductive layer and the other electrode of a second conductive layer, and disposing the first conductive layer adjacently thereto. CONSTITUTION:The lower electrode of a laminated capacity is formed of a polysilicon layer 3 connected to the source 11a of a FET in a memory cell 1, and of another polysilicon layer 4 connected to that in a memory cell 2, and the layers 3, 4 are alternately employed in a perpendicular direction to this paper. They are isolated in the cells by a connecting hole 14 to a bit line 15, and its interval R is small like on an isolating layer 12 in other boundary. Accordingly, they can be easily integrated. The ends of the layers 3, 4 cover the sidewalls of a gate electrode 16 to widen its area. An interlayer insulating film 18 is formed on each lower electrode, a common capacity upper electrode 19 is superposed, and a bit line 15 is disposed through an interlayer insulating film 20. According to this configuration, the pattern of the layers 3, 4 is reduced like a size R1, and can be extended to the vicinity of the boundary of the cells, thereby increasing its lower area to increase its capacity. Accordingly, even if a memory size is reduced, the characteric of the cell can be secured.