JPS6449176A - Pll circuit - Google Patents
Pll circuitInfo
- Publication number
- JPS6449176A JPS6449176A JP62205015A JP20501587A JPS6449176A JP S6449176 A JPS6449176 A JP S6449176A JP 62205015 A JP62205015 A JP 62205015A JP 20501587 A JP20501587 A JP 20501587A JP S6449176 A JPS6449176 A JP S6449176A
- Authority
- JP
- Japan
- Prior art keywords
- frequency
- comparator
- capture range
- signal
- shear
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000010355 oscillation Effects 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/087—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
Landscapes
- Signal Processing For Digital Recording And Reproducing (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
PURPOSE:To expand a capture range by controlling a voltage control oscillator also by the output of a frequency comparator in addition to the output of a phase comparator. CONSTITUTION:When a frequency difference between an 8/10 signal inputted from a terminal 1 as a reference input and a demodulating clock as a variable input is stored in the 1st capture range, a phase comparator 3 compares both the inputs and outputs an error signal having size and polarity corresponding to the shear, quantity and directions of the phases. When said frequency difference is stored in the 2nd capture range wider than the 1st range, a frequency comparator 4 compares both the values and outputs the shear or the like of frequency as a signal. High frequency components are respectively removed from signals obtained from comparators 3, 4 by the 1st and 2nd LPFs 5, 6, inputted to an adder 7, controlled by the oscillation frequency of a voltage control oscillator 8 and outputted from a terminal 2 as a demodulated clock.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62205015A JPH0719440B2 (en) | 1987-08-20 | 1987-08-20 | PLL circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62205015A JPH0719440B2 (en) | 1987-08-20 | 1987-08-20 | PLL circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6449176A true JPS6449176A (en) | 1989-02-23 |
JPH0719440B2 JPH0719440B2 (en) | 1995-03-06 |
Family
ID=16500033
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP62205015A Expired - Lifetime JPH0719440B2 (en) | 1987-08-20 | 1987-08-20 | PLL circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0719440B2 (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH042217A (en) * | 1990-04-19 | 1992-01-07 | Nec Corp | Pll frequency synthesizer |
JPH06268516A (en) * | 1993-03-12 | 1994-09-22 | Nec Corp | Method for clock subordinate synchronization |
US6496555B1 (en) | 1998-07-22 | 2002-12-17 | Nec Corporation | Phase locked loop |
-
1987
- 1987-08-20 JP JP62205015A patent/JPH0719440B2/en not_active Expired - Lifetime
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH042217A (en) * | 1990-04-19 | 1992-01-07 | Nec Corp | Pll frequency synthesizer |
JPH06268516A (en) * | 1993-03-12 | 1994-09-22 | Nec Corp | Method for clock subordinate synchronization |
US6496555B1 (en) | 1998-07-22 | 2002-12-17 | Nec Corporation | Phase locked loop |
Also Published As
Publication number | Publication date |
---|---|
JPH0719440B2 (en) | 1995-03-06 |
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