JPS6447063A - Structure of lead frame - Google Patents

Structure of lead frame

Info

Publication number
JPS6447063A
JPS6447063A JP20480287A JP20480287A JPS6447063A JP S6447063 A JPS6447063 A JP S6447063A JP 20480287 A JP20480287 A JP 20480287A JP 20480287 A JP20480287 A JP 20480287A JP S6447063 A JPS6447063 A JP S6447063A
Authority
JP
Japan
Prior art keywords
island
frame
bonding
chip element
cut
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP20480287A
Other languages
Japanese (ja)
Inventor
Kenji Uesugi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rohm Co Ltd
Original Assignee
Rohm Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rohm Co Ltd filed Critical Rohm Co Ltd
Priority to JP20480287A priority Critical patent/JPS6447063A/en
Publication of JPS6447063A publication Critical patent/JPS6447063A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To enable obliteration of a defective wire bonding by a method wherein an island connecting section of a first frame is made to be connected with an island with a chip element which is cut off from a second frame with an island where a chip element is previously bonded. CONSTITUTION:A first frame 1 provided with inner leads 5 and an island connecting section 6 and an island with a chip element, which is cut off from a second frame 8 with an island 10 where a chip element C is previously bonded, to be connected with the island connecting section 6 constitute a lead frame. In a manufacturing process of a semiconductor device, the first frame 1 provided with inner leads 5...is made to be connected with the island 10 already die- bonded which is cut off from the second frame 8, when a process is shifted to the next wire-bonding process. That is, when a die-bonding is performed, the inner leads 5 are prevented from oxidation due to the heat which is released when the island 10 is heated. Therefore, the defective wire-bonding taking place due to the thermal effect based on a wire-bonding is obliterated.
JP20480287A 1987-08-18 1987-08-18 Structure of lead frame Pending JPS6447063A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20480287A JPS6447063A (en) 1987-08-18 1987-08-18 Structure of lead frame

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20480287A JPS6447063A (en) 1987-08-18 1987-08-18 Structure of lead frame

Publications (1)

Publication Number Publication Date
JPS6447063A true JPS6447063A (en) 1989-02-21

Family

ID=16496606

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20480287A Pending JPS6447063A (en) 1987-08-18 1987-08-18 Structure of lead frame

Country Status (1)

Country Link
JP (1) JPS6447063A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5637917A (en) * 1995-09-20 1997-06-10 Mitsubishi Denki Kabushiki Kaisha Lead frame assembly for a semiconductor device
JP2014049584A (en) * 2012-08-31 2014-03-17 Shindengen Electric Mfg Co Ltd Lead frame and manufacturing method of resin-sealed semiconductor device
JP2015138796A (en) * 2014-01-20 2015-07-30 新電元工業株式会社 Lead frame and manufacturing method of the same
JP2015138795A (en) * 2014-01-20 2015-07-30 新電元工業株式会社 Lead frame and manufacturing method of the same

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60149154A (en) * 1984-01-17 1985-08-06 Nec Corp Manufacture of semiconductor device
JPS62205653A (en) * 1986-03-06 1987-09-10 Mitsui Haitetsuku:Kk Manufacture of lead frame and semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60149154A (en) * 1984-01-17 1985-08-06 Nec Corp Manufacture of semiconductor device
JPS62205653A (en) * 1986-03-06 1987-09-10 Mitsui Haitetsuku:Kk Manufacture of lead frame and semiconductor device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5637917A (en) * 1995-09-20 1997-06-10 Mitsubishi Denki Kabushiki Kaisha Lead frame assembly for a semiconductor device
JP2014049584A (en) * 2012-08-31 2014-03-17 Shindengen Electric Mfg Co Ltd Lead frame and manufacturing method of resin-sealed semiconductor device
JP2015138796A (en) * 2014-01-20 2015-07-30 新電元工業株式会社 Lead frame and manufacturing method of the same
JP2015138795A (en) * 2014-01-20 2015-07-30 新電元工業株式会社 Lead frame and manufacturing method of the same

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