JPS6445155A - Memory integrated circuit - Google Patents

Memory integrated circuit

Info

Publication number
JPS6445155A
JPS6445155A JP62202929A JP20292987A JPS6445155A JP S6445155 A JPS6445155 A JP S6445155A JP 62202929 A JP62202929 A JP 62202929A JP 20292987 A JP20292987 A JP 20292987A JP S6445155 A JPS6445155 A JP S6445155A
Authority
JP
Japan
Prior art keywords
integrated circuit
memory
memory integrated
chip
memories
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62202929A
Other languages
Japanese (ja)
Inventor
Hiroshi Nakajima
Ueji Koyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
NEC Engineering Ltd
Original Assignee
NEC Corp
NEC Engineering Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, NEC Engineering Ltd filed Critical NEC Corp
Priority to JP62202929A priority Critical patent/JPS6445155A/en
Publication of JPS6445155A publication Critical patent/JPS6445155A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Dram (AREA)
  • Die Bonding (AREA)
  • Semiconductor Memories (AREA)

Abstract

PURPOSE:To facilitate a high degree of integration by a method wherein vertical multiple chip composition is applied to chip mounting. CONSTITUTION:A vertical multiple chip is composed of memories 1, 2, i.e., the memories 1, 2 are block constituents of the title memory integrated circuit and in case the chip select 3 is 'L', the memory 1 is to be selected, while in case the chip select 3 is 'H', the memory 2 is to be selected. Through these procedures, the circuit can be easily integrated to a high degree.
JP62202929A 1987-08-13 1987-08-13 Memory integrated circuit Pending JPS6445155A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62202929A JPS6445155A (en) 1987-08-13 1987-08-13 Memory integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62202929A JPS6445155A (en) 1987-08-13 1987-08-13 Memory integrated circuit

Publications (1)

Publication Number Publication Date
JPS6445155A true JPS6445155A (en) 1989-02-17

Family

ID=16465496

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62202929A Pending JPS6445155A (en) 1987-08-13 1987-08-13 Memory integrated circuit

Country Status (1)

Country Link
JP (1) JPS6445155A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5172358A (en) * 1989-03-08 1992-12-15 Yamaha Corporation Loudness control circuit for an audio device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5172358A (en) * 1989-03-08 1992-12-15 Yamaha Corporation Loudness control circuit for an audio device

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