JPS6441046A - Fault processing system for address conversion buffer - Google Patents

Fault processing system for address conversion buffer

Info

Publication number
JPS6441046A
JPS6441046A JP62196930A JP19693087A JPS6441046A JP S6441046 A JPS6441046 A JP S6441046A JP 62196930 A JP62196930 A JP 62196930A JP 19693087 A JP19693087 A JP 19693087A JP S6441046 A JPS6441046 A JP S6441046A
Authority
JP
Japan
Prior art keywords
fault
address conversion
address
degeneration
conversion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62196930A
Other languages
Japanese (ja)
Inventor
Kozo Yamano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62196930A priority Critical patent/JPS6441046A/en
Publication of JPS6441046A publication Critical patent/JPS6441046A/en
Pending legal-status Critical Current

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  • Debugging And Monitoring (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

PURPOSE:To avoid the degeneration due to occurrence of a fault by writing a real address calculated with retrieval of an address conversion table in a logical address supplied when the fault is detected into an entry corresponding to the input logical address. CONSTITUTION:When a fault is detected by a fault detecting circuit 9 at conversion between the logical and real addresses, an address conversion control circuit 6 performs again the conversion of addresses with retrieval of an address conversion table of a memory 14. Then the circuit 6 carries out continuously such retry processing where the result of address conversion is registered again in the entry where the fault occurred up to the prescribed frequency. In such a way, the intermittent faults of an address conversion buffer part 3 are relieved. Thus it is possible to avoid the degeneration of the part 3 before a fault occurs after the retry processing is carried out up to the prescribed frequency. Then the deterioration of the system performance due to the degeneration of the part 3 can be reduced.
JP62196930A 1987-08-06 1987-08-06 Fault processing system for address conversion buffer Pending JPS6441046A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62196930A JPS6441046A (en) 1987-08-06 1987-08-06 Fault processing system for address conversion buffer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62196930A JPS6441046A (en) 1987-08-06 1987-08-06 Fault processing system for address conversion buffer

Publications (1)

Publication Number Publication Date
JPS6441046A true JPS6441046A (en) 1989-02-13

Family

ID=16366026

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62196930A Pending JPS6441046A (en) 1987-08-06 1987-08-06 Fault processing system for address conversion buffer

Country Status (1)

Country Link
JP (1) JPS6441046A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5878278A (en) * 1994-10-03 1999-03-02 International Business Machines Corporation System for controlling connection requests by each IO controllers storing and managing a request queue wherein additional channel addresses can be added

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5878278A (en) * 1994-10-03 1999-03-02 International Business Machines Corporation System for controlling connection requests by each IO controllers storing and managing a request queue wherein additional channel addresses can be added

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