JPS6439654U - - Google Patents

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本考案の一実施例を示すＣＭＯＳ回路
の概略構成図、第２図はその寄生トランジスタの
等価回路図、第３図は第１図の平面図に相当する
パターンレイアウト図、第４図は入力保護回路の
一例を示すブロツク図、第５図はその概略構成図
、第６図は第５図の入力保護回路に本考案を適用
した構成を示す図、第７図は従来例であるＣＭＯ
Ｓ回路の概略構成図、第８図はその寄生トランジ
スタの等価回路図である。 １：Ｎ形半導体基板、２：ＰチヤネルＭＯＳＦ
ＥＴのＰ^＋ソース領域、３：Ｐウエル、４：Ｎチ
ヤネルＭＯＳＦＥＴのソース領域、７，８：ガー
ドバンド、３０：ＰチヤネルＭＯＳＦＥＴ、４０
：ＮチヤネルＭＯＳＦＥＴ、５１：パツド、５３
：Ｐウエル、５４：Ｐ^＋コンタクト領域。 FIG. 1 is a schematic configuration diagram of a CMOS circuit showing an embodiment of the present invention, FIG. 2 is an equivalent circuit diagram of its parasitic transistor, FIG. 3 is a pattern layout diagram corresponding to the plan view of FIG. 1, and FIG. Figure 5 is a block diagram showing an example of an input protection circuit, Figure 5 is a schematic configuration diagram thereof, Figure 6 is a diagram showing a configuration in which the present invention is applied to the input protection circuit in Figure 5, and Figure 7 is a conventional example. A CMO
A schematic configuration diagram of the S circuit, and FIG. 8 is an equivalent circuit diagram of its parasitic transistor. 1: N-type semiconductor substrate, 2: P-channel MOSF
ET P ⁺ source region, 3: P well, 4: N channel MOSFET source region, 7, 8: guard band, 30: P channel MOSFET, 40
:N channel MOSFET, 51: Padded, 53
:P well, 54:P ⁺ contact region.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 一導電形の半導体基板と、この半導体基板内に
形成された逆導電形の第１のウエルと、この第１
のウエルに形成された第１の素子と、前記半導体
基板上に形成され第１の素子とは相補関係の第２
の素子と、前記第１の素子と第２の素子との間の
前記半導体基板内に形成された逆導電形の第２の
ウエルとを具備し、この第２のウエルを所定電位
に接続したことを特徴とする半導体装置。 a semiconductor substrate of one conductivity type; a first well of an opposite conductivity type formed in the semiconductor substrate;
The first element formed in the well and the second element formed on the semiconductor substrate are complementary to each other.
and a second well of an opposite conductivity type formed in the semiconductor substrate between the first element and the second element, the second well being connected to a predetermined potential. A semiconductor device characterized by: