JPS6439538U - - Google Patents
Info
- Publication number
- JPS6439538U JPS6439538U JP13289287U JP13289287U JPS6439538U JP S6439538 U JPS6439538 U JP S6439538U JP 13289287 U JP13289287 U JP 13289287U JP 13289287 U JP13289287 U JP 13289287U JP S6439538 U JPS6439538 U JP S6439538U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- write signal
- control circuit
- write
- peripheral device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000001360 synchronised effect Effects 0.000 claims description 5
- 230000002093 peripheral effect Effects 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 6
- 230000004069 differentiation Effects 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
Description
第１図は本考案に係るデータ書込み回路の一実
施例を示すブロツク図、第２図は第１図に示した
同期微分回路の回路図、第３図は本考案に係る他
の実施例を示すブロツク図、第４図は第１図から
第３図のタイミングチヤートを示す図、第５図は
従来例のブロツク図、第６図は第５図のタイミン
グチヤートを示す図である。
１１，２１，３１……制御回路（ＣＰＵ）、１
２，２２，３２……デコード回路、１３，２３，
３３……周辺装置、２４，３４……同期微分回路
、２５，２６……フリツプフロツプ、２７……負
論理アンド回路、ＴＳＴ……データ安定時間、Ｔ
Ｄ……書込み信号遅延時間、Ｔｈ……データホー
ルド時間。
FIG. 1 is a block diagram showing one embodiment of the data writing circuit according to the present invention, FIG. 2 is a circuit diagram of the synchronous differential circuit shown in FIG. 1, and FIG. 3 is a block diagram showing another embodiment according to the present invention. 4 is a diagram showing the timing chart of FIGS. 1 to 3, FIG. 5 is a block diagram of the conventional example, and FIG. 6 is a diagram showing the timing chart of FIG. 5. 11, 21, 31...control circuit (CPU), 1
2, 22, 32... decoding circuit, 13, 23,
33... Peripheral device, 24, 34... Synchronous differentiation circuit, 25, 26... Flip-flop, 27... Negative logic AND circuit, TST... Data stabilization time, T
D...Write signal delay time, Th ...Data hold time.
Claims (1)
に書込み信号を出力し、該書込み信号にもとづき
前記制御回路から出力するデータを前記周辺装置
に書き込むデータ書込み回路において、 前記書込み信号を前記制御回路のシステムクロ
ツクの変化タイミングにもとづいて同期微分する
同期微分回路 を具えたことを特徴とするデータ書込み回路。 (2) 前記同期微分回路は、アドレス指定されて
周辺装置に入力する書込み信号を同期微分するこ
とを特徴とする実用新案登録請求の範囲第(1)項
記載のデータ書込み回路。 (3) 前記同期微分回路は、制御回路から出力す
る書込み信号を同期微分することを特徴とする実
用新案登録請求の範囲第(1)項記載のデータ書込
み回路。[Claims for Utility Model Registration] (1) A data write circuit that outputs a write signal from a control circuit to a peripheral device designated by an address, and writes data output from the control circuit to the peripheral device based on the write signal, A data write circuit comprising a synchronous differentiator for synchronously differentiating the write signal based on a change timing of a system clock of the control circuit. (2) The data write circuit according to claim (1), wherein the synchronous differentiator synchronously differentiates a write signal that is addressed and input to a peripheral device. (3) The data write circuit according to claim 1, wherein the synchronous differentiator synchronously differentiates the write signal output from the control circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13289287U JPS6439538U (en) | 1987-08-31 | 1987-08-31 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13289287U JPS6439538U (en) | 1987-08-31 | 1987-08-31 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6439538U true JPS6439538U (en) | 1989-03-09 |
Family
ID=31390274
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13289287U Pending JPS6439538U (en) | 1987-08-31 | 1987-08-31 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6439538U (en) |
-
1987
- 1987-08-31 JP JP13289287U patent/JPS6439538U/ja active Pending
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