JPS6438664A - Holding circuit - Google Patents

Holding circuit

Info

Publication number
JPS6438664A
JPS6438664A JP62194165A JP19416587A JPS6438664A JP S6438664 A JPS6438664 A JP S6438664A JP 62194165 A JP62194165 A JP 62194165A JP 19416587 A JP19416587 A JP 19416587A JP S6438664 A JPS6438664 A JP S6438664A
Authority
JP
Japan
Prior art keywords
switch
voltage
turned
circuit
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62194165A
Other languages
Japanese (ja)
Inventor
Fumihide Murao
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP62194165A priority Critical patent/JPS6438664A/en
Publication of JPS6438664A publication Critical patent/JPS6438664A/en
Pending legal-status Critical Current

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  • Measurement Of Current Or Voltage (AREA)

Abstract

PURPOSE:To obtain a holding circuit capable of converging the output of a buffer circuit to predetermined voltage an infinite time after holding is started, by providing the switch, resistor and power source connected to a holding capacitor (C) in series and controlling said switch during a holding state by the pulse signal of a pulse generating circuit. CONSTITUTION:When a switch 2 is turned ON by the signal from a control terminal 3 and a switch 6 is turned OFF by a pulse generating circuit 9, the voltage of an input terminal 1 is outputted to the output of a buffer circuit 5. Next, when the switch 2 is turned OFF by the signal from the terminal 2 and the switch 6 is turned ON and OFF by the pulse signal from the circuit 9, the voltage immediately before the switch 2 is turned OFF preserved in C4 is outputted to the output of the circuit 5 immediately after the switch 2 is turned OFF. The current calculated by dividing the difference voltage of the voltage of a power supply 8 and the voltage held to C4 by the resistance value of a resistor 7 is charged in and discharged from C4 only during a time when the switch 6 is turned ON and, after the definite time determined by the pulse width of the circuit 9 and the resistance value of the resistor 7, the voltage between both terminals thereof becomes the same voltage as the power source 8 and the output of the circuit 5 becomes the same voltage as the power supply 8.
JP62194165A 1987-08-03 1987-08-03 Holding circuit Pending JPS6438664A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62194165A JPS6438664A (en) 1987-08-03 1987-08-03 Holding circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62194165A JPS6438664A (en) 1987-08-03 1987-08-03 Holding circuit

Publications (1)

Publication Number Publication Date
JPS6438664A true JPS6438664A (en) 1989-02-08

Family

ID=16320010

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62194165A Pending JPS6438664A (en) 1987-08-03 1987-08-03 Holding circuit

Country Status (1)

Country Link
JP (1) JPS6438664A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0411399A (en) * 1990-04-27 1992-01-16 Nec Corp Sample-and-hold amplifier circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0411399A (en) * 1990-04-27 1992-01-16 Nec Corp Sample-and-hold amplifier circuit

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