JPS6436118A - Digital pulse width modulator - Google Patents

Digital pulse width modulator

Info

Publication number
JPS6436118A
JPS6436118A JP19049687A JP19049687A JPS6436118A JP S6436118 A JPS6436118 A JP S6436118A JP 19049687 A JP19049687 A JP 19049687A JP 19049687 A JP19049687 A JP 19049687A JP S6436118 A JPS6436118 A JP S6436118A
Authority
JP
Japan
Prior art keywords
order
bit
pulse width
input data
low
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP19049687A
Other languages
Japanese (ja)
Inventor
Kaoru Inoue
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mazda Motor Corp
Original Assignee
Mazda Motor Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mazda Motor Corp filed Critical Mazda Motor Corp
Priority to JP19049687A priority Critical patent/JPS6436118A/en
Publication of JPS6436118A publication Critical patent/JPS6436118A/en
Pending legal-status Critical Current

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  • Analogue/Digital Conversion (AREA)

Abstract

PURPOSE:To obtain a pulse width modulation output signal with less pulse uneven distribution by providing a 2nd comparator circuit receiving the weight of each digit of a high-order n-bit of a free run counter while revising in a prescribed order and comparing it with a low-order n-bit of an input data. CONSTITUTION:A 1st comparator 4 comparing the low-order n-bit of the free run counter 2 with the high-order n-bit of the input data and outputting a 1st binary signal, and the 2nd comparator 3 comparing the high-order n-bit of the free counter 3 with the low-order n-bit of the input data while revising the weight of each digit of the high-order n-bit in a prescribed order and outputting a 2nd binary signal are provided. Thus, the 2nd binary signal is the result of pulse width modulation of the low-order bit data of the input data and is located between the two 1st binary signals, then the uneven distribution of the pulse width modulation signal of the output is prevented.
JP19049687A 1987-07-31 1987-07-31 Digital pulse width modulator Pending JPS6436118A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19049687A JPS6436118A (en) 1987-07-31 1987-07-31 Digital pulse width modulator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19049687A JPS6436118A (en) 1987-07-31 1987-07-31 Digital pulse width modulator

Publications (1)

Publication Number Publication Date
JPS6436118A true JPS6436118A (en) 1989-02-07

Family

ID=16259060

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19049687A Pending JPS6436118A (en) 1987-07-31 1987-07-31 Digital pulse width modulator

Country Status (1)

Country Link
JP (1) JPS6436118A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0353041U (en) * 1989-09-27 1991-05-22
US5576730A (en) * 1992-04-08 1996-11-19 Sharp Kabushiki Kaisha Active matrix substrate and a method for producing the same
US6310913B1 (en) 1996-05-20 2001-10-30 Asahi Kasei Kabushiki Kaisha Circuit and method for modulating pulse width
JP2020108007A (en) * 2018-12-27 2020-07-09 アダマンド並木精密宝石株式会社 Pulse width modulation circuit

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5539499A (en) * 1978-09-06 1980-03-19 Siemens Ag Method of and device for converting digital to analog
JPS57155833A (en) * 1981-03-23 1982-09-27 Toshiba Corp Digital-to-analog converting circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5539499A (en) * 1978-09-06 1980-03-19 Siemens Ag Method of and device for converting digital to analog
JPS57155833A (en) * 1981-03-23 1982-09-27 Toshiba Corp Digital-to-analog converting circuit

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0353041U (en) * 1989-09-27 1991-05-22
US5576730A (en) * 1992-04-08 1996-11-19 Sharp Kabushiki Kaisha Active matrix substrate and a method for producing the same
US6310913B1 (en) 1996-05-20 2001-10-30 Asahi Kasei Kabushiki Kaisha Circuit and method for modulating pulse width
JP2020108007A (en) * 2018-12-27 2020-07-09 アダマンド並木精密宝石株式会社 Pulse width modulation circuit

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