JPS6436046A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS6436046A JPS6436046A JP19190387A JP19190387A JPS6436046A JP S6436046 A JPS6436046 A JP S6436046A JP 19190387 A JP19190387 A JP 19190387A JP 19190387 A JP19190387 A JP 19190387A JP S6436046 A JPS6436046 A JP S6436046A
- Authority
- JP
- Japan
- Prior art keywords
- silicon
- crystal
- substrate
- layer
- solid growth
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Recrystallisation Techniques (AREA)
Abstract
PURPOSE:To manufacture a semiconductor having an SOI structure which suppresses leakage at an interface by a method wherein an insulating film layer composed of CaF2 or SrF2 is deposited on a singlecrystal silicon substrate, surface silicon is laminated, the surface of the substrate is made amorphous by an ion implantation operation and three layers which have been made amorphous by a solid growth method are made crystalline. CONSTITUTION:Si ions 5 are implanted into a silicon substrate 1; a surface region of the silicon substrate 1, a CaF2 film 2 and a silicon film 3 are made amorphous; single crystal CaF2 6 and singlecrystal silicon 7 are formed on the single-crystal silicon substrate 1 by a solid growth method by using a heat treatment or by irradiation with a beam of light, an ion or an electron. According to this manufacturing method, an interface between an amorphous region and a single-crystal region at an initial stage of the growth operation is situated in a surface region of the substrate 1; a defect 8 caused during the solid growth operation exists only in the substrate 1. Accordingly, a defect density of the surface single-crystal silicon layer 7 forming a device is very small. Because a lattice constant of the insulating crystal 6 is close to that of the single-crystal silicon 7 during the solid growth operation, the mismatching at the interface between the layer 6 and the layer 7 can be suppressed.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP19190387A JPS6436046A (en) | 1987-07-31 | 1987-07-31 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP19190387A JPS6436046A (en) | 1987-07-31 | 1987-07-31 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6436046A true JPS6436046A (en) | 1989-02-07 |
Family
ID=16282365
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP19190387A Pending JPS6436046A (en) | 1987-07-31 | 1987-07-31 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6436046A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1037272A1 (en) * | 1997-06-19 | 2000-09-20 | Asahi Kasei Kogyo Kabushiki Kaisha | Soi substrate and process for preparing the same, and semiconductor device and process for preparing the same |
JP2005524987A (en) * | 2002-05-07 | 2005-08-18 | エーエスエム アメリカ インコーポレイテッド | Silicon-on-insulator structure and manufacturing method thereof |
-
1987
- 1987-07-31 JP JP19190387A patent/JPS6436046A/en active Pending
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1037272A1 (en) * | 1997-06-19 | 2000-09-20 | Asahi Kasei Kogyo Kabushiki Kaisha | Soi substrate and process for preparing the same, and semiconductor device and process for preparing the same |
US6528387B1 (en) | 1997-06-19 | 2003-03-04 | Asahi Kasei Kabushiki Kaisha | SOI substrate and process for preparing the same, and semiconductor device and process for preparing the same |
EP1037272A4 (en) * | 1997-06-19 | 2004-07-28 | Asahi Chemical Ind | Soi substrate and process for preparing the same, and semiconductor device and process for preparing the same |
JP2005524987A (en) * | 2002-05-07 | 2005-08-18 | エーエスエム アメリカ インコーポレイテッド | Silicon-on-insulator structure and manufacturing method thereof |
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