JPS64350U - - Google Patents
Info
- Publication number
- JPS64350U JPS64350U JP1987094053U JP9405387U JPS64350U JP S64350 U JPS64350 U JP S64350U JP 1987094053 U JP1987094053 U JP 1987094053U JP 9405387 U JP9405387 U JP 9405387U JP S64350 U JPS64350 U JP S64350U
- Authority
- JP
- Japan
- Prior art keywords
- light emitting
- emitting diode
- conductive pattern
- chip
- model registration
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000011347 resin Substances 0.000 claims description 3
- 229920005989 resin Polymers 0.000 claims description 3
- 239000000758 substrate Substances 0.000 claims description 3
- 239000003973 paint Substances 0.000 claims description 2
- 238000000034 method Methods 0.000 claims 1
- 238000000465 moulding Methods 0.000 claims 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000000463 material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Description
第1図及び第2図は本考案に係る発光ダイオー
ドの一実施例を示す断面図、第3図〜第6図は本
考案の他の実施例を示す断面図、第7図及び第8
図は従来例を示す正面図及び断面図である。
1……ボンデイング用基板、1A……基材、1
B……導電パターン、2……LEDチツプ、3…
…極細金線、4……樹脂、5及び6……リング状
の囲い。
1 and 2 are cross-sectional views showing one embodiment of a light emitting diode according to the present invention, FIGS. 3 to 6 are cross-sectional views showing other embodiments of the present invention, and FIGS. 7 and 8 are cross-sectional views showing other embodiments of the present invention.
The figures are a front view and a sectional view showing a conventional example. 1...Bonding substrate, 1A...Base material, 1
B... Conductive pattern, 2... LED chip, 3...
...Ultra-fine gold wire, 4...Resin, 5 and 6...Ring-shaped enclosure.
補正 昭63.2.18
実用新案登録請求の範囲を次のように補正する
。Amendment February 18, 1983 The scope of claims for utility model registration is amended as follows.
【実用新案登録請求の範囲】
所要の導電パターンを形成したボンデイング用
基板にLEDチツプをダイボンデイングし、ワイ
ヤボンデイングを行つた後、樹脂モールド処理な
どを施すようにした発光ダイオードにおいて、L
EDチツプの周りに導電パターン自体、基板に凹
部を設け、または白色系塗料により囲いを形成し
反射効果をもたせたことを特徴とする発光ダイオ
ード。[Claims for Utility Model Registration] A light emitting diode in which an LED chip is die-bonded to a bonding substrate on which a required conductive pattern is formed, wire bonded, and then resin molded, etc.
The conductive pattern itself , a recess on the board, or a white paint surround the ED chip.
A light emitting diode characterized by having a reflective effect .
Claims (1)
基板にLEDチツプをダイボンデイングし、ワイ
ヤボンデイングを行つた後、樹脂モールド処理な
どを施すようにした発光ダイオードにおいて、L
EDチツプの周りに導電パターン自体または白色
系塗料により囲いを形成したことを特徴とする発
光ダイオード。 In a light emitting diode, an LED chip is die-bonded to a bonding substrate on which a required conductive pattern is formed, wire bonding is performed, and then a resin molding process is performed.
A light emitting diode characterized in that an enclosure is formed around an ED chip using the conductive pattern itself or white paint.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1987094053U JPS64350U (en) | 1987-06-19 | 1987-06-19 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1987094053U JPS64350U (en) | 1987-06-19 | 1987-06-19 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS64350U true JPS64350U (en) | 1989-01-05 |
Family
ID=30957148
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1987094053U Pending JPS64350U (en) | 1987-06-19 | 1987-06-19 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS64350U (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008270733A (en) * | 2007-04-23 | 2008-11-06 | Augux Co Ltd | Packaging method of led with high heat conducting efficiency and its structure |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6054175B2 (en) * | 1978-11-24 | 1985-11-29 | 積水化学工業株式会社 | Continuous foam extrusion equipment |
JPS611066A (en) * | 1984-06-13 | 1986-01-07 | Stanley Electric Co Ltd | Molding method of led chip mounted on printed board |
JPS62185382A (en) * | 1986-02-08 | 1987-08-13 | Copal Co Ltd | Light emitting element array |
-
1987
- 1987-06-19 JP JP1987094053U patent/JPS64350U/ja active Pending
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6054175B2 (en) * | 1978-11-24 | 1985-11-29 | 積水化学工業株式会社 | Continuous foam extrusion equipment |
JPS611066A (en) * | 1984-06-13 | 1986-01-07 | Stanley Electric Co Ltd | Molding method of led chip mounted on printed board |
JPS62185382A (en) * | 1986-02-08 | 1987-08-13 | Copal Co Ltd | Light emitting element array |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008270733A (en) * | 2007-04-23 | 2008-11-06 | Augux Co Ltd | Packaging method of led with high heat conducting efficiency and its structure |
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