JPS643330U - - Google Patents
Info
- Publication number
- JPS643330U JPS643330U JP9632687U JP9632687U JPS643330U JP S643330 U JPS643330 U JP S643330U JP 9632687 U JP9632687 U JP 9632687U JP 9632687 U JP9632687 U JP 9632687U JP S643330 U JPS643330 U JP S643330U
- Authority
- JP
- Japan
- Prior art keywords
- analog signal
- level
- reference value
- signal
- binarization circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000003247 decreasing effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 4
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 1
Landscapes
- Manipulation Of Pulses (AREA)
Description
第１図は本考案の一実施例を示す回路図。第２
図および第３図ａ，ｂ，ｃは本考案の一実施例に
おける動作を示す波形図。第４図は従来の２値化
回路を示す回路図。第５図ａ，ｂは従来の２値化
回路における波形図。
符号の説明、１……演算増幅器、２……アナロ
グ信号入力端子、３……ダイオード、４，５……
コンパレータ、５，７……出力端子、６……ＯＲ
回路、１０……原稿読取信号発生回路、１１……
原稿、１２……発光ダイオード、１３……ホトト
ランジスタ、１４，１５，１７……演算増幅器、
１６……ダイオード、１８……読取信号出力端子
、２０……２値化回路。
FIG. 1 is a circuit diagram showing an embodiment of the present invention. Second
3A, 3B, and 3C are waveform diagrams showing the operation in one embodiment of the present invention. FIG. 4 is a circuit diagram showing a conventional binarization circuit. FIGS. 5a and 5b are waveform diagrams in a conventional binarization circuit. Explanation of symbols, 1...Operation amplifier, 2...Analog signal input terminal, 3...Diode, 4, 5...
Comparator, 5, 7...output terminal, 6...OR
Circuit, 10... Original reading signal generation circuit, 11...
Original, 12... Light emitting diode, 13... Phototransistor, 14, 15, 17... Operational amplifier,
16... Diode, 18... Read signal output terminal, 20... Binarization circuit.
Claims (1)
る２値化回路において、 前記アナログ信号の微細な変化を無視してその
レベルに追従して変化する浮動スレツシユホール
ド信号を前記基準値とする第１の比較手段と、 予め定めた固定基準値を前記基準値とする第２
の比較手段を備えたことを特徴とするアナログ信
号の２値化回路。 (2) 前記第２の比較手段が、前記浮動スレツシ
ユホールド信号が前記微細な変化を無視して追従
するアナログ信号のレベルと、レベル低下によつ
て信号変化に忠実に追従するアナログ信号のレベ
ルとの間に前記固定基準値のレベルを設定する構
成の実用新案登録請求の範囲第１項記載のアナロ
グ信号の２値化回路。[Claims for Utility Model Registration] (1) In a binarization circuit that binarizes an analog signal by comparing it with a reference value, a floating signal that ignores minute changes in the analog signal and changes to follow its level. a first comparison means that uses a threshold signal as the reference value; and a second comparison means that uses a predetermined fixed reference value as the reference value.
What is claimed is: 1. An analog signal binarization circuit characterized by comprising a comparing means. (2) The second comparing means compares the level of the analog signal that the floating threshold signal follows while ignoring the minute changes, and the level of the analog signal that faithfully follows the signal change by decreasing the level. 2. The analog signal binarization circuit according to claim 1, wherein the level of the fixed reference value is set between .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987096326U JPH0731623Y2 (en) | 1987-06-23 | 1987-06-23 | Binary circuit for original reading signal |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987096326U JPH0731623Y2 (en) | 1987-06-23 | 1987-06-23 | Binary circuit for original reading signal |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS643330U true JPS643330U (en) | 1989-01-10 |
| JPH0731623Y2 JPH0731623Y2 (en) | 1995-07-19 |
Family
ID=31321204
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1987096326U Expired - Lifetime JPH0731623Y2 (en) | 1987-06-23 | 1987-06-23 | Binary circuit for original reading signal |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0731623Y2 (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5582535A (en) * | 1978-12-19 | 1980-06-21 | Toshiba Corp | Automatic threshold value control circuit |
| JPS5689125A (en) * | 1979-12-21 | 1981-07-20 | Fuji Electric Co Ltd | Binary circuit |
-
1987
- 1987-06-23 JP JP1987096326U patent/JPH0731623Y2/en not_active Expired - Lifetime
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5582535A (en) * | 1978-12-19 | 1980-06-21 | Toshiba Corp | Automatic threshold value control circuit |
| JPS5689125A (en) * | 1979-12-21 | 1981-07-20 | Fuji Electric Co Ltd | Binary circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0731623Y2 (en) | 1995-07-19 |
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