JPS6433268U - - Google Patents
Info
- Publication number
- JPS6433268U JPS6433268U JP12902887U JP12902887U JPS6433268U JP S6433268 U JPS6433268 U JP S6433268U JP 12902887 U JP12902887 U JP 12902887U JP 12902887 U JP12902887 U JP 12902887U JP S6433268 U JPS6433268 U JP S6433268U
- Authority
- JP
- Japan
- Prior art keywords
- control terminal
- power
- turned
- video
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 claims description 2
- 230000001681 protective effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Television Receiver Circuits (AREA)
Description
第１図は本考案を実施した白ピーク制限回路の
回路図である。第２図は従来例の回路図である。
１……映像処理回路、２……映像出力端子、３
……映像出力回路、４……コントラスト制御端子
、６……自動輝度制限回路、Ｄ……スイツチング
ダイオード、Ｒ３……保護用抵抗、Ｃ２……コン
デンサ。
FIG. 1 is a circuit diagram of a white peak limiting circuit implementing the present invention. FIG. 2 is a circuit diagram of a conventional example. 1...Video processing circuit, 2...Video output terminal, 3
...Video output circuit, 4...Contrast control terminal, 6...Automatic brightness limiting circuit, D...Switching diode, R3 ...Protection resistor, C2 ...Capacitor.
Claims (1)
子を有する映像処理回路と、前記制御端子を制御
するように接続された自動輝度制限回路と、前記
出力端子に接続された映像出力回路と、前記制御
端子と前記映像出力回路間に接続され電源投入時
に導通して前記制御端子の電圧を下げるように動
作するスイツチング手段とを有する回路において
、前記スイツチング手段に直列に接続された保護
用抵抗に並列に、電源投入時における前記出力回
路の白ピーク信号を前記制御端子側へ落すための
コンデンサを接続したことを特徴とする電源投入
時における白ピーク制限回路。 a video processing circuit having a contrast control terminal and a video signal output terminal; an automatic brightness limiting circuit connected to control the control terminal; a video output circuit connected to the output terminal; and a switching means connected between the video output circuits and operating to conduct when the power is turned on to lower the voltage at the control terminal, wherein a power supply is connected in parallel to a protective resistor connected in series to the switching means. A white peak limiting circuit when power is turned on, characterized in that a capacitor is connected to drop a white peak signal of the output circuit to the control terminal side when the power is turned on.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12902887U JPS6433268U (en) | 1987-08-25 | 1987-08-25 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12902887U JPS6433268U (en) | 1987-08-25 | 1987-08-25 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6433268U true JPS6433268U (en) | 1989-03-01 |
Family
ID=31382921
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12902887U Pending JPS6433268U (en) | 1987-08-25 | 1987-08-25 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6433268U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0454559U (en) * | 1990-09-07 | 1992-05-11 |
-
1987
- 1987-08-25 JP JP12902887U patent/JPS6433268U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0454559U (en) * | 1990-09-07 | 1992-05-11 |
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