JPS6432525A - Semiconductor logic circuit - Google Patents

Semiconductor logic circuit

Info

Publication number
JPS6432525A
JPS6432525A JP62189322A JP18932287A JPS6432525A JP S6432525 A JPS6432525 A JP S6432525A JP 62189322 A JP62189322 A JP 62189322A JP 18932287 A JP18932287 A JP 18932287A JP S6432525 A JPS6432525 A JP S6432525A
Authority
JP
Japan
Prior art keywords
turned
falling
output signal
state
bipolar
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62189322A
Other languages
Japanese (ja)
Inventor
Isao Fukushi
Setsu Nomura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu VLSI Ltd
Fujitsu Ltd
Original Assignee
Fujitsu VLSI Ltd
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu VLSI Ltd, Fujitsu Ltd filed Critical Fujitsu VLSI Ltd
Priority to JP62189322A priority Critical patent/JPS6432525A/en
Publication of JPS6432525A publication Critical patent/JPS6432525A/en
Pending legal-status Critical Current

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  • Electronic Switches (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE:To quicken the falling of an output signal by detecting a transient current caused due to parasitic capacitance of a bipolar transistor(TR) caused at the time of rising and providing a TR falling its output signal in response thereto. CONSTITUTION:A transient current Ipass flowing through a parasitic capacitor CCB at the time of rising and only at transient state is detected by a forward internal resistor of a diode 18 and fed to a TR 19. Thus, the TR 19 is turned on, a current Idis flows to the ground and the potential at an output terminal OUT goes immediately to a low level together with a TR 17 turned on simultaneously. Then an output signal is kept low by the ON-state of a 2nd bipolar TR 17 and the ON-state of the MOS TR 15 with a 2nd MOS gate circuit 21 turned on thereby increasing the falling responsiveness considerably. Thus, the transient current flowing uselessly for the charging/discharging of the CCB of a 1st bipolar TR 16 is utilized effectively to improve the performance of the logic circuit.
JP62189322A 1987-07-28 1987-07-28 Semiconductor logic circuit Pending JPS6432525A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62189322A JPS6432525A (en) 1987-07-28 1987-07-28 Semiconductor logic circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62189322A JPS6432525A (en) 1987-07-28 1987-07-28 Semiconductor logic circuit

Publications (1)

Publication Number Publication Date
JPS6432525A true JPS6432525A (en) 1989-02-02

Family

ID=16239419

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62189322A Pending JPS6432525A (en) 1987-07-28 1987-07-28 Semiconductor logic circuit

Country Status (1)

Country Link
JP (1) JPS6432525A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003066313A (en) * 2001-08-29 2003-03-05 Nikon Corp Optical device
DE102010052717B4 (en) 2009-11-26 2021-11-11 Fanuc Corporation Method for controlling a spot welding system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003066313A (en) * 2001-08-29 2003-03-05 Nikon Corp Optical device
DE102010052717B4 (en) 2009-11-26 2021-11-11 Fanuc Corporation Method for controlling a spot welding system

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