JPS6431442A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS6431442A
JPS6431442A JP18820187A JP18820187A JPS6431442A JP S6431442 A JPS6431442 A JP S6431442A JP 18820187 A JP18820187 A JP 18820187A JP 18820187 A JP18820187 A JP 18820187A JP S6431442 A JPS6431442 A JP S6431442A
Authority
JP
Japan
Prior art keywords
layer
width
silicon
active region
polycrystalline silicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18820187A
Other languages
Japanese (ja)
Inventor
Kazuo Tanaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP18820187A priority Critical patent/JPS6431442A/en
Publication of JPS6431442A publication Critical patent/JPS6431442A/en
Pending legal-status Critical Current

Links

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To miniaturize an element without increasing the width of a polycrystalline silicon at a hole by forming the width of a polycrystalline silicon layer for bringing into contact with a silicide layer formed on an active region on a silicon substrate surrounded by an insulator at a value equal to or less than the width of the silicide layer. CONSTITUTION:The four sides of the active region 101 of a semiconductor substrate 100 is surrounded by an insulating film 102, such as a silicon oxide film, and a silicon nitride film, and a silicide layer 103 is formed on the opening 104 of the active region. Then, when the polycrystalline silicon is etched, the silicon substrate of the active region of an element for obtaining the etching selection ratio of 5:1 is not etched between a polycrystalline silicon layer 105 and the layer 103, it is not necessary to increase the width of the silicon layer, and the width of the silicon layer can be formed at a value less than the width of the layer 103 when the active region of the element is brought into contact with the layer 105 through the opening 104. Accordingly, the element can be miniaturized without increasing the width of the polycrystalline silicon.
JP18820187A 1987-07-28 1987-07-28 Semiconductor device Pending JPS6431442A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18820187A JPS6431442A (en) 1987-07-28 1987-07-28 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18820187A JPS6431442A (en) 1987-07-28 1987-07-28 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS6431442A true JPS6431442A (en) 1989-02-01

Family

ID=16219544

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18820187A Pending JPS6431442A (en) 1987-07-28 1987-07-28 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS6431442A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5707770A (en) * 1994-11-08 1998-01-13 Canon Kabushiki Kaisha Toner for developing electrostatic images, two component type developer, developing method, image forming method, heat fixing method, and process for producing toner

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5707770A (en) * 1994-11-08 1998-01-13 Canon Kabushiki Kaisha Toner for developing electrostatic images, two component type developer, developing method, image forming method, heat fixing method, and process for producing toner
US5824442A (en) * 1994-11-08 1998-10-20 Canon Kabushiki Kaisha Developing method, image forming method, and heat fixing method, with toner

Similar Documents

Publication Publication Date Title
US4758530A (en) Doubly-self-aligned hole-within-a-hole structure in semiconductor fabrication involving a double LOCOS process aligned with sidewall spacers
JPS55163860A (en) Manufacture of semiconductor device
EP0288052A3 (en) Semiconductor device comprising a substrate, and production method thereof
US4131909A (en) Semiconductor integrated circuit isolated through dielectric material and a method for manufacturing the same
US5369052A (en) Method of forming dual field oxide isolation
KR940012647A (en) Semiconductor integrated circuit device and manufacturing method thereof
JPS5799777A (en) Metal oxide semiconductor type semiconductor device
EP0029552A3 (en) Method for producing a semiconductor device
US5053345A (en) Method of edge doping SOI islands
US4658495A (en) Method of forming a semiconductor structure
JPS5696865A (en) Manufacture of semiconductor device
JPS6431442A (en) Semiconductor device
JPS57191539A (en) Semiconductor ion sensor
JPS6420663A (en) Manufacture of semiconductor device
JPS5575238A (en) Method of fabricating semiconductor device
JPS52117079A (en) Preparation of semiconductor device
JPS6425475A (en) Mos type semiconductor device
EP0067738A3 (en) Method of reducing encroachment in a semiconductor device
JPS6467975A (en) Semiconductor device and manufacture thereof
JPS64761A (en) Semiconductor device
JPS6421940A (en) Manufacture of semiconductor device
JPS644048A (en) Manufacture of semiconductor integrated circuit
JPS55111172A (en) Nonvolatile semiconductor memory device
JPS6476739A (en) Manufacture of semiconductor device
JPS5627970A (en) Semiconductor device