JPS6428973A - Member for mounting optical semiconductor element chip - Google Patents

Member for mounting optical semiconductor element chip

Info

Publication number
JPS6428973A
JPS6428973A JP18594987A JP18594987A JPS6428973A JP S6428973 A JPS6428973 A JP S6428973A JP 18594987 A JP18594987 A JP 18594987A JP 18594987 A JP18594987 A JP 18594987A JP S6428973 A JPS6428973 A JP S6428973A
Authority
JP
Japan
Prior art keywords
solder layer
semiconductor element
layer
element chip
optical semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18594987A
Other languages
Japanese (ja)
Inventor
Mitsuo Ishii
Kazuyoshi Hasegawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP18594987A priority Critical patent/JPS6428973A/en
Publication of JPS6428973A publication Critical patent/JPS6428973A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/4901—Structure
    • H01L2224/4903—Connectors having different sizes, e.g. different diameters
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Led Device Packages (AREA)
  • Led Devices (AREA)
  • Die Bonding (AREA)

Abstract

PURPOSE:To realize incessantly good junction and mounting of an optical semiconductor element chip, by using an evaporation method to form a solder layer in a shape corresponding to that of the optical semiconductor element chip to be mounted. CONSTITUTION:A solder layer 8 is formed in a shape corresponding to that of a semiconductor element chip 7 to be mounted, in the nearly central position of one side on a surface of an electrical wiring layer 3 located on a surface side. Formation of this solder layer 8 is performed by using a lift-off method for metallic layer evaporation as follows. First a photoresist is piled throughout the surface except the part where the solder layer 8 is formed on the electrode wiring layer 3. Second the solder layer is evaporated on the whole surface. Finally the photoresist is removed to make only the solder layer 8 remain on the electrical wiring layer 3. Also the evaporation method is used to form a solder layer 9 on the whole surface of the electrical wiring layer 3 positioned on the rear side. An electrode layer 10 is junctioned on the solder layer 8 positioned on the surface side of a mounting member 1 formed in this way, and the optical semiconductor element chip 7 is mounted thereon.
JP18594987A 1987-07-24 1987-07-24 Member for mounting optical semiconductor element chip Pending JPS6428973A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18594987A JPS6428973A (en) 1987-07-24 1987-07-24 Member for mounting optical semiconductor element chip

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18594987A JPS6428973A (en) 1987-07-24 1987-07-24 Member for mounting optical semiconductor element chip

Publications (1)

Publication Number Publication Date
JPS6428973A true JPS6428973A (en) 1989-01-31

Family

ID=16179696

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18594987A Pending JPS6428973A (en) 1987-07-24 1987-07-24 Member for mounting optical semiconductor element chip

Country Status (1)

Country Link
JP (1) JPS6428973A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007273744A (en) * 2006-03-31 2007-10-18 Stanley Electric Co Ltd Eutectic crystal substrate for led, and method for manufacturing the same

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5998566A (en) * 1982-11-26 1984-06-06 Nec Corp Heat sink
JPS59159583A (en) * 1983-03-02 1984-09-10 Hitachi Ltd Semiconductor light emitting device
JPS59167038A (en) * 1983-03-14 1984-09-20 Hitachi Ltd Structure of submount for photo semiconductor element

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5998566A (en) * 1982-11-26 1984-06-06 Nec Corp Heat sink
JPS59159583A (en) * 1983-03-02 1984-09-10 Hitachi Ltd Semiconductor light emitting device
JPS59167038A (en) * 1983-03-14 1984-09-20 Hitachi Ltd Structure of submount for photo semiconductor element

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007273744A (en) * 2006-03-31 2007-10-18 Stanley Electric Co Ltd Eutectic crystal substrate for led, and method for manufacturing the same

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