JPS6424632A - Phase locked loop circuit - Google Patents

Phase locked loop circuit

Info

Publication number
JPS6424632A
JPS6424632A JP62179935A JP17993587A JPS6424632A JP S6424632 A JPS6424632 A JP S6424632A JP 62179935 A JP62179935 A JP 62179935A JP 17993587 A JP17993587 A JP 17993587A JP S6424632 A JPS6424632 A JP S6424632A
Authority
JP
Japan
Prior art keywords
frequency
circuit
vco
signal
360mhz
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62179935A
Other languages
Japanese (ja)
Inventor
Fumihiko Kobayashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP62179935A priority Critical patent/JPS6424632A/en
Publication of JPS6424632A publication Critical patent/JPS6424632A/en
Pending legal-status Critical Current

Links

Landscapes

  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

PURPOSE:To prevent spurious radiation with a comparatively simple circuit constitution by providing a signal suppressing circuit means eliminating a frequency component being (n)-fold of the frequency of an input signal, and further, as required, 1/n-fold between a low pass filter and a voltage controlled oscillation circuit VCO. CONSTITUTION:The signal suppression circuit 3a composed of an adder circuit 32 and a delay circuit 31 whose delay time (tau) is 1/2fr is provided on a post- stage of a phase comparator 11 and a low pass filter 12, and its output signal is applied to the VCO 14. A frequency divider 15 is connected between the VCO 14 and the phase comparator 11. The input frequency 10MHz is FM- modulated by the VCO 14 to become an output signal SOUT in a frequency of 360MHz. On the other hand, a spurious component is outputted at a position deviated by 10MHz at both sides of the frequency of 360MHz, but it is removed.
JP62179935A 1987-07-21 1987-07-21 Phase locked loop circuit Pending JPS6424632A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62179935A JPS6424632A (en) 1987-07-21 1987-07-21 Phase locked loop circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62179935A JPS6424632A (en) 1987-07-21 1987-07-21 Phase locked loop circuit

Publications (1)

Publication Number Publication Date
JPS6424632A true JPS6424632A (en) 1989-01-26

Family

ID=16074509

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62179935A Pending JPS6424632A (en) 1987-07-21 1987-07-21 Phase locked loop circuit

Country Status (1)

Country Link
JP (1) JPS6424632A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8253469B2 (en) 2008-09-30 2012-08-28 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
JP2015039179A (en) * 2002-08-28 2015-02-26 クゥアルコム・インコーポレイテッドＱｕａｌｃｏｍｍ Ｉｎｃｏｒｐｏｒａｔｅｄ Method and apparatus for phase locked loop

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015039179A (en) * 2002-08-28 2015-02-26 クゥアルコム・インコーポレイテッドＱｕａｌｃｏｍｍ Ｉｎｃｏｒｐｏｒａｔｅｄ Method and apparatus for phase locked loop
US8253469B2 (en) 2008-09-30 2012-08-28 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device

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