JPS6424510A - Preventing circuit for malfunction of up/down counter - Google Patents

Preventing circuit for malfunction of up/down counter

Info

Publication number
JPS6424510A
JPS6424510A JP62180449A JP18044987A JPS6424510A JP S6424510 A JPS6424510 A JP S6424510A JP 62180449 A JP62180449 A JP 62180449A JP 18044987 A JP18044987 A JP 18044987A JP S6424510 A JPS6424510 A JP S6424510A
Authority
JP
Japan
Prior art keywords
down counter
flip
clock signal
flop
control signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62180449A
Other languages
Japanese (ja)
Inventor
Tadanori Nakayama
Masaru Hashirano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP62180449A priority Critical patent/JPS6424510A/en
Publication of JPS6424510A publication Critical patent/JPS6424510A/en
Pending legal-status Critical Current

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  • Pulse Circuits (AREA)

Abstract

PURPOSE:To prevent an up/down counter from malfunctioning even if an asynchronous clock signal or up/down control signal is inputted by counting the outputs of two flip-flop circuits which delay the output of a 1st flip-flop circuit by a constant time and controlling the counting direction of the up/down counter. CONSTITUTION:The up/down counter inputs a clock signal to be counted by the 1st flip-flop circuit 4 to normalize the clock signal and also inputs the up/ down control signal for controlling the up/down mode of the up/down counter 7 by a 3rd flip-flop 6 to match the up/down control signal with the normalized clock signal. Then the normalized clock signal is delayed by the 2nd flip-flop circuit 5, the output of the 3rd flip-flop circuit 6 is used as the up/down control signal of the up/down counter 7, and the output of the 2nd flip-flop 5 is used as the clock signal of the up/down counter 7. Consequently, the up/down counter is prevented from malfunctioning.
JP62180449A 1987-07-20 1987-07-20 Preventing circuit for malfunction of up/down counter Pending JPS6424510A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62180449A JPS6424510A (en) 1987-07-20 1987-07-20 Preventing circuit for malfunction of up/down counter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62180449A JPS6424510A (en) 1987-07-20 1987-07-20 Preventing circuit for malfunction of up/down counter

Publications (1)

Publication Number Publication Date
JPS6424510A true JPS6424510A (en) 1989-01-26

Family

ID=16083426

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62180449A Pending JPS6424510A (en) 1987-07-20 1987-07-20 Preventing circuit for malfunction of up/down counter

Country Status (1)

Country Link
JP (1) JPS6424510A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62106771A (en) * 1978-07-20 1987-05-18 バクスター、インターナショナル、インコーポレイテッド Improved seal member of membrane diffusion apparatus

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62106771A (en) * 1978-07-20 1987-05-18 バクスター、インターナショナル、インコーポレイテッド Improved seal member of membrane diffusion apparatus

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