JPS6423498A - Eeprom - Google Patents
EepromInfo
- Publication number
- JPS6423498A JPS6423498A JP18039687A JP18039687A JPS6423498A JP S6423498 A JPS6423498 A JP S6423498A JP 18039687 A JP18039687 A JP 18039687A JP 18039687 A JP18039687 A JP 18039687A JP S6423498 A JPS6423498 A JP S6423498A
- Authority
- JP
- Japan
- Prior art keywords
- nmos
- latch
- inverter
- circuit
- sense line
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Read Only Memory (AREA)
Abstract
PURPOSE:To reduce the quantity to a supply power to a latch inverter and to suppress the increase of a circuit occupying area by serially connecting a control transistor controlled by a clock signal to the latch inverter. CONSTITUTION:A page latch circuit has a sense line 101 and bit lines 102-0-102-7, a sense line data latch circuit 103 is connected to the sense line 101 and bit line data latch circuits 104-0-104-7 are connected to the respective bit lines. In the latch inverter of a latch circuit 103a consisting of an NMOS 111 and an NMOS 112 and the latch inverter of a latch circuit 104a consisting of an NMOS 121 and an NMOS 122, the control transistors NMOS 119 and NMOS 129 controlled by the clock signal phi100 are serially disposed. Thereby, during the L level period of the signal phi100, the supply of a power to the inverter can be stopped, the supply power can be reduced, and the increase in the circuit occupying area can be suppressed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18039687A JPS6423498A (en) | 1987-07-20 | 1987-07-20 | Eeprom |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18039687A JPS6423498A (en) | 1987-07-20 | 1987-07-20 | Eeprom |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6423498A true JPS6423498A (en) | 1989-01-26 |
Family
ID=16082505
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18039687A Pending JPS6423498A (en) | 1987-07-20 | 1987-07-20 | Eeprom |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6423498A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1997038423A1 (en) * | 1996-04-05 | 1997-10-16 | Advanced Micro Devices, Inc. | Parallel page buffer verify or read of cells on a word line using a signal from a reference cell in a flash memory device |
| JP2007136315A (en) * | 2005-11-17 | 2007-06-07 | East Japan Railway Co | Atmosphere shielding apparatus in liquid receiving tank |
-
1987
- 1987-07-20 JP JP18039687A patent/JPS6423498A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1997038423A1 (en) * | 1996-04-05 | 1997-10-16 | Advanced Micro Devices, Inc. | Parallel page buffer verify or read of cells on a word line using a signal from a reference cell in a flash memory device |
| JP2007136315A (en) * | 2005-11-17 | 2007-06-07 | East Japan Railway Co | Atmosphere shielding apparatus in liquid receiving tank |
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