JPS6421440U - - Google Patents
Info
- Publication number
- JPS6421440U JPS6421440U JP11488387U JP11488387U JPS6421440U JP S6421440 U JPS6421440 U JP S6421440U JP 11488387 U JP11488387 U JP 11488387U JP 11488387 U JP11488387 U JP 11488387U JP S6421440 U JPS6421440 U JP S6421440U
- Authority
- JP
- Japan
- Prior art keywords
- channel control
- control device
- operate
- devices
- parallel
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000012544 monitoring process Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 5
Description
第1図は本考案のI/Oチヤネル制御装置を用
いたシステムを表わす構成を表わす図、第2図は
本考案のI/Oチヤネル制御装置を表わす構成図
、第3図は本考案装置を用いたシステムの動作を
表す図、第4図は従来のI/Oチヤネル制御装置
を用いたシステムを表わす図である。
1…ホスト計算機、2…システム・バス、3…
I/Oチヤネル制御装置、4…磁気デイスク、5
…磁気テープ、6…プリンタ、7…I/Oバス、
14…デイスク・ドライバ、15…テープ・ドラ
イバ、16…プリンタ・ドライバ、311…シス
テム・バス・インターフエイス、312…I/O
バス・インターフエイス、313…マイクロプロ
セツサMPU、321,322,〜,32n,8
…タイマ。
Fig. 1 is a diagram showing the configuration of a system using the I/O channel control device of the present invention, Fig. 2 is a block diagram showing the I/O channel control device of the present invention, and Fig. 3 is a diagram showing the configuration of a system using the I/O channel control device of the present invention. FIG. 4 is a diagram showing the operation of the system used. FIG. 4 is a diagram showing a system using a conventional I/O channel control device. 1...Host computer, 2...System bus, 3...
I/O channel control device, 4...magnetic disk, 5
...Magnetic tape, 6...Printer, 7...I/O bus,
14...Disk driver, 15...Tape driver, 16...Printer driver, 311...System bus interface, 312...I/O
Bus interface, 313...Microprocessor MPU, 321, 322, ~, 32n, 8
...Timer.
Claims (1)
のデバイスをシステム・バスを介してホスト計算
機に接続するI/Oチヤネル制御装置において、
並行動作可能なデバイス個数分のタイマを設け、
現在タイムアウトを監視しているデバイスが動作
を中断した場合は、他のデバイスを並行動作させ
てこのデバイスのタイムアウト監視を行なうこと
を特徴とするI/Oチヤネル制御装置。 In an I/O channel control device that connects a plurality of devices having a standardized interface to a host computer via a system bus,
Set up timers for the number of devices that can operate in parallel,
An I/O channel control device characterized in that when a device currently monitoring a timeout interrupts its operation, it causes another device to operate in parallel to monitor the timeout of this device.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11488387U JPH0512823Y2 (en) | 1987-07-27 | 1987-07-27 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11488387U JPH0512823Y2 (en) | 1987-07-27 | 1987-07-27 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6421440U true JPS6421440U (en) | 1989-02-02 |
JPH0512823Y2 JPH0512823Y2 (en) | 1993-04-05 |
Family
ID=31356031
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP11488387U Expired - Lifetime JPH0512823Y2 (en) | 1987-07-27 | 1987-07-27 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0512823Y2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2001052073A1 (en) * | 2000-01-13 | 2001-07-19 | Sony Computer Entertainment Inc. | Interface device and information processing system comprising it |
-
1987
- 1987-07-27 JP JP11488387U patent/JPH0512823Y2/ja not_active Expired - Lifetime
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2001052073A1 (en) * | 2000-01-13 | 2001-07-19 | Sony Computer Entertainment Inc. | Interface device and information processing system comprising it |
Also Published As
Publication number | Publication date |
---|---|
JPH0512823Y2 (en) | 1993-04-05 |
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