JPS6420717A - Synchronizing signal generator - Google Patents

Synchronizing signal generator

Info

Publication number
JPS6420717A
JPS6420717A JP17801487A JP17801487A JPS6420717A JP S6420717 A JPS6420717 A JP S6420717A JP 17801487 A JP17801487 A JP 17801487A JP 17801487 A JP17801487 A JP 17801487A JP S6420717 A JPS6420717 A JP S6420717A
Authority
JP
Japan
Prior art keywords
fet
frequency
output
double
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17801487A
Other languages
Japanese (ja)
Inventor
Satoshi Kimura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP17801487A priority Critical patent/JPS6420717A/en
Publication of JPS6420717A publication Critical patent/JPS6420717A/en
Pending legal-status Critical Current

Links

Landscapes

  • Synchronisation In Digital Transmission Systems (AREA)
  • Manipulation Of Pulses (AREA)

Abstract

PURPOSE:To widen the frequency band with simple constitution and small size by using a double multiplication means so as to double the signal frequency and obtaining a timing clock. CONSTITUTION:An NRZ signal coming from an input terminal 1 and amplified by a preamplifier 2 is given to an FET 5. The FET 5, based on the NRZ signal, generates a harmonic wave being multiplying the frequency of the signal twice. The output of the FET 5 is given to a tank circuit 8, which extracts only the harmonic component doubled in the output of the FET 5 and gives an output. Thus, the timing clock having a double frequency of that of the NRZ signal is obtained from an output terminal 10. In this case, the FET 5 is operative up to an ultrahigh frequency and the frequency band is widened with simple constitution.
JP17801487A 1987-07-16 1987-07-16 Synchronizing signal generator Pending JPS6420717A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17801487A JPS6420717A (en) 1987-07-16 1987-07-16 Synchronizing signal generator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17801487A JPS6420717A (en) 1987-07-16 1987-07-16 Synchronizing signal generator

Publications (1)

Publication Number Publication Date
JPS6420717A true JPS6420717A (en) 1989-01-24

Family

ID=16041055

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17801487A Pending JPS6420717A (en) 1987-07-16 1987-07-16 Synchronizing signal generator

Country Status (1)

Country Link
JP (1) JPS6420717A (en)

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