JPS6418756U - - Google Patents
Info
- Publication number
- JPS6418756U JPS6418756U JP11427687U JP11427687U JPS6418756U JP S6418756 U JPS6418756 U JP S6418756U JP 11427687 U JP11427687 U JP 11427687U JP 11427687 U JP11427687 U JP 11427687U JP S6418756 U JPS6418756 U JP S6418756U
- Authority
- JP
- Japan
- Prior art keywords
- film
- substrate
- gate electrode
- insulating film
- baking
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000010408 film Substances 0.000 claims description 11
- 239000000758 substrate Substances 0.000 claims description 5
- 239000010409 thin film Substances 0.000 claims description 5
- 239000004065 semiconductor Substances 0.000 claims description 2
- 238000000151 deposition Methods 0.000 claims 1
- 239000012212 insulator Substances 0.000 claims 1
- -1 silanol compound Chemical class 0.000 claims 1
- 150000003377 silicon compounds Chemical class 0.000 claims 1
- 238000004528 spin coating Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 2
Landscapes
- Liquid Crystal (AREA)
- Thin Film Transistor (AREA)
Description
第１図は本考案の一実施例に係る薄膜トランジ
スタの構造を示す図、第２図ａ〜ｃは本考案の薄
膜トランジスタの一実施例に係る製造工程を示す
図、第３図ａ〜ｃは従来の薄膜トランジスタの製
造工程を示す図である。
１１……基板、１２……ゲート電極、１３……
ＳＯＧ膜、１４……絶縁膜、１５……半導体膜、
１７……ソース電極、１８……ドレイン電極。
Figure 1 is a diagram showing the structure of a thin film transistor according to an embodiment of the present invention, Figures 2 a to c are diagrams showing the manufacturing process of an embodiment of the thin film transistor of the present invention, and Figures 3 a to c are conventional FIG. 3 is a diagram showing the manufacturing process of the thin film transistor of FIG. 11...Substrate, 12...Gate electrode, 13...
SOG film, 14... Insulating film, 15... Semiconductor film,
17...source electrode, 18...drain electrode.
補正 昭６２．１１．４
図面の簡単な説明を次のように補正する。
明細書第１２頁第１７行目に「ソース」とある
を「ドレイン」と補正する。
明細書第１２頁第１８行目に「ドレイン」とあ
るを「ソース」と補正する。Amendment November 4, 1982 The brief description of the drawing is amended as follows. On page 12, line 17 of the specification, the word "source" is corrected to read "drain." On page 12, line 18 of the specification, the word "drain" is corrected to "source."
Claims (1)
面上及びゲート電極面上にけい素化合物を、前記
基板面上の膜厚より前記ゲート電極面上の膜厚の
方を薄く塗布し、焼成して形成された第１の絶縁
膜と、この第１の絶縁膜上に絶縁物を堆積して形
成された第２の絶縁膜と、この第２の絶縁膜上に
順次形成された半導体膜及び電極とを備えたこと
を特徴とする薄膜トランジスタ。 (2) 前記第１の絶縁膜は、前記基板及びゲート
電極上にシラノール系化合物溶液を、スピンコー
トにより塗布し、焼成することにより形成されて
いることを特徴とする実用新案登録請求の範囲第
１項記載の薄膜トランジスタ。[Claims for Utility Model Registration] (1) A substrate on which a gate electrode is formed, and a silicon compound on the surface of this substrate and the surface of the gate electrode, and a film on the gate electrode surface that is thicker than the film on the substrate surface. A first insulating film formed by applying a thinner layer and baking it; a second insulating film formed by depositing an insulator on this first insulating film; A thin film transistor comprising a semiconductor film and an electrode sequentially formed on the film. (2) The first insulating film is formed by applying a silanol compound solution onto the substrate and the gate electrode by spin coating, and then baking it. The thin film transistor according to item 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987114276U JPH079388Y2 (en) | 1987-07-25 | 1987-07-25 | Thin film transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987114276U JPH079388Y2 (en) | 1987-07-25 | 1987-07-25 | Thin film transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6418756U true JPS6418756U (en) | 1989-01-30 |
| JPH079388Y2 JPH079388Y2 (en) | 1995-03-06 |
Family
ID=31354873
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1987114276U Expired - Lifetime JPH079388Y2 (en) | 1987-07-25 | 1987-07-25 | Thin film transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH079388Y2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008287266A (en) * | 2006-03-15 | 2008-11-27 | Sharp Corp | Active matrix substrate, display device and television receiver |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5192189A (en) * | 1975-02-10 | 1976-08-12 | Handotaisochi no seizohoho | |
| JPS5633899A (en) * | 1979-08-29 | 1981-04-04 | Cho Lsi Gijutsu Kenkyu Kumiai | Method of forming multilayer wire |
| JPS58182270A (en) * | 1982-04-16 | 1983-10-25 | Sanyo Electric Co Ltd | Manufacture of transistor |
| JPS58201364A (en) * | 1982-05-20 | 1983-11-24 | Matsushita Electric Ind Co Ltd | Semiconductor device and manufacture thereof |
-
1987
- 1987-07-25 JP JP1987114276U patent/JPH079388Y2/en not_active Expired - Lifetime
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5192189A (en) * | 1975-02-10 | 1976-08-12 | Handotaisochi no seizohoho | |
| JPS5633899A (en) * | 1979-08-29 | 1981-04-04 | Cho Lsi Gijutsu Kenkyu Kumiai | Method of forming multilayer wire |
| JPS58182270A (en) * | 1982-04-16 | 1983-10-25 | Sanyo Electric Co Ltd | Manufacture of transistor |
| JPS58201364A (en) * | 1982-05-20 | 1983-11-24 | Matsushita Electric Ind Co Ltd | Semiconductor device and manufacture thereof |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008287266A (en) * | 2006-03-15 | 2008-11-27 | Sharp Corp | Active matrix substrate, display device and television receiver |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH079388Y2 (en) | 1995-03-06 |
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