JPS6417294A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To erase all the contents of a memory at a high speed by providing a data line pre-charge signal control circuit, a sense amplifier driving signal control circuit, and a counter circuit. CONSTITUTION:The titled memory is provided with circuits L2, L3 for holding sense amplifier driving signals phiSA, -phiSA in an active state in order to hold a sense amplifier SA in an operating state, while the contents of a memory MC are erased, a circuit L1 for holding a data pre-charge signal -phiPC in a non-active state, and a circuit AC for generating an address signal Axi in the inside of a chip in order to select and drive successively a word line W, during that time. In this state, the data line pre-charge signal is held in a non-active state, an erasion use data written in the memory cell MC connected to the word line determined in advance is held by the sense amplifier SA by holding the sense amplifier driving signal in an active state, and by operating the address signal generating circuit AC, the word line is activated successively. In such a way, whenever the word line is selected and driven, the contents of plural memory cells connected thereto are erased, and the erasion time can be remarkably shortened.