JPS6416079A - Noise reduction circuit - Google Patents

Noise reduction circuit

Info

Publication number
JPS6416079A
JPS6416079A JP62171797A JP17179787A JPS6416079A JP S6416079 A JPS6416079 A JP S6416079A JP 62171797 A JP62171797 A JP 62171797A JP 17179787 A JP17179787 A JP 17179787A JP S6416079 A JPS6416079 A JP S6416079A
Authority
JP
Japan
Prior art keywords
signal
level
limiter
adder
suppressed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62171797A
Other languages
Japanese (ja)
Inventor
Masaru Nonogaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP62171797A priority Critical patent/JPS6416079A/en
Publication of JPS6416079A publication Critical patent/JPS6416079A/en
Pending legal-status Critical Current

Links

Landscapes

  • Picture Signal Circuits (AREA)
  • Filters That Use Time-Delay Elements (AREA)

Abstract

PURPOSE:To make noise unremarkable when a pattern is moving by suppressing an output signal if a signal of one field difference or one frame difference exceeds a prescribed level. CONSTITUTION:If an input signal S1 has a moving component, a level of a signal S3 exceeds + or -V1 and the signal S3 is subject to amplitude limit by a limiter 6. In this case, a detection circuit 9 detects limiter ON and a control voltage generating circuit 10 generates a control signal S7 of a prescribed level in response to the etection signal. The signal S7 is subtracted from the control signal S5 at an adder 11. Thus, the position signal S8 (=S5) outputted at a period without movement so far from the adder 11 is decreased by a quantity of the signal S7. Thus, one of the gain of an amplifier 5, the DC level and the frequency characteristic is at least suppressed and at least one of brightness on the screen, contrast and sharpness is suppressed, the noise appearing attended with the movement of the pattern is made unremarkable.
JP62171797A 1987-07-09 1987-07-09 Noise reduction circuit Pending JPS6416079A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62171797A JPS6416079A (en) 1987-07-09 1987-07-09 Noise reduction circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62171797A JPS6416079A (en) 1987-07-09 1987-07-09 Noise reduction circuit

Publications (1)

Publication Number Publication Date
JPS6416079A true JPS6416079A (en) 1989-01-19

Family

ID=15929878

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62171797A Pending JPS6416079A (en) 1987-07-09 1987-07-09 Noise reduction circuit

Country Status (1)

Country Link
JP (1) JPS6416079A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63234674A (en) * 1987-03-23 1988-09-29 Nec Home Electronics Ltd Noise reduction device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63234674A (en) * 1987-03-23 1988-09-29 Nec Home Electronics Ltd Noise reduction device

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