JPS6414795A - Semiconductor storage device - Google Patents

Semiconductor storage device

Info

Publication number
JPS6414795A
JPS6414795A JP62168659A JP16865987A JPS6414795A JP S6414795 A JPS6414795 A JP S6414795A JP 62168659 A JP62168659 A JP 62168659A JP 16865987 A JP16865987 A JP 16865987A JP S6414795 A JPS6414795 A JP S6414795A
Authority
JP
Japan
Prior art keywords
phias
selectively
timing signal
dynamic type
type ram
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62168659A
Other languages
Japanese (ja)
Inventor
Kyoko Ishii
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP62168659A priority Critical patent/JPS6414795A/en
Publication of JPS6414795A publication Critical patent/JPS6414795A/en
Pending legal-status Critical Current

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  • Dram (AREA)

Abstract

PURPOSE:To attain rapid I/O operation to/from all memory cells by providing the titled device with a function for selectively fetching only a prescribed low address signal for selecting a memory array by combining control signals supplied from the external by a prescribed method. CONSTITUTION:Two X-address signals AXi-1, AXi consisting of upper 2 bits are fetched into an array selecting circuit ASL through a low address buffer RADB in accordance with a timing signal phias and held. When a dynamic type RAM is in a page mode, the timing signal phias is selectively and independently formed. At that time, the dynamic type RAM is kept at a selected state. Thus, the timing signal phias is independently formed and the row address consisting of upper 2 bits is selectively fetched. Consequently, the dynamic type RAM can execute a rapid access mode such as a page mode over all the memory arrays.
JP62168659A 1987-07-08 1987-07-08 Semiconductor storage device Pending JPS6414795A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62168659A JPS6414795A (en) 1987-07-08 1987-07-08 Semiconductor storage device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62168659A JPS6414795A (en) 1987-07-08 1987-07-08 Semiconductor storage device

Publications (1)

Publication Number Publication Date
JPS6414795A true JPS6414795A (en) 1989-01-18

Family

ID=15872120

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62168659A Pending JPS6414795A (en) 1987-07-08 1987-07-08 Semiconductor storage device

Country Status (1)

Country Link
JP (1) JPS6414795A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05182452A (en) * 1991-12-27 1993-07-23 Nec Corp High speed dynamic random access memory device
US6034911A (en) * 1995-10-13 2000-03-07 Nec Corporation Semiconductor memory device for a rapid random access
WO2005004164A1 (en) * 2003-06-30 2005-01-13 Fujitsu Limited Semiconductor storage device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05182452A (en) * 1991-12-27 1993-07-23 Nec Corp High speed dynamic random access memory device
US6034911A (en) * 1995-10-13 2000-03-07 Nec Corporation Semiconductor memory device for a rapid random access
WO2005004164A1 (en) * 2003-06-30 2005-01-13 Fujitsu Limited Semiconductor storage device
US7102960B2 (en) 2003-06-30 2006-09-05 Fujitsu Limited Semiconductor memory device

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