JPS6413262A - Digital sound recording device - Google Patents

Digital sound recording device

Info

Publication number
JPS6413262A
JPS6413262A JP16931387A JP16931387A JPS6413262A JP S6413262 A JPS6413262 A JP S6413262A JP 16931387 A JP16931387 A JP 16931387A JP 16931387 A JP16931387 A JP 16931387A JP S6413262 A JPS6413262 A JP S6413262A
Authority
JP
Japan
Prior art keywords
signal
level
multiplier
calculation
digital signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP16931387A
Other languages
Japanese (ja)
Other versions
JPH0770155B2 (en
Inventor
Toru Saito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Group Corp
Original Assignee
Aiwa Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Aiwa Co Ltd filed Critical Aiwa Co Ltd
Priority to JP16931387A priority Critical patent/JPH0770155B2/en
Publication of JPS6413262A publication Critical patent/JPS6413262A/en
Publication of JPH0770155B2 publication Critical patent/JPH0770155B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Landscapes

  • Signal Processing For Digital Recording And Reproducing (AREA)

Abstract

PURPOSE:To automatically make the level of an input analog signal optimum by controlling a multiplication factor value while comparing digitally a signal that the output from an A/D converter is multiplied by a factor with a digital signal containing a reference signal. CONSTITUTION:The digital signal Sd for level comparison is inputted to a level controlling means 40. Besides, the analog signal to be recorded is adjusted by a level adjusting means 13 so as to be somewhat large and after being digitized by the A/D converter, it is inputted to a multiplier 46. The multiplier 46 stores the output signal Sa of itself and the above-mentioned signal Sd for a duration necessitated for calculation and in addition, inputs the signal Sa to the controlling means 40. The means 40 obtains a comparison output corresponding to a level difference for the signal Sd and inputs the new factor value to the multiplier 46 through a factor adjuster 45, and the multiplier 46 executes a calculation for correction and outputs the signal Sa. This calculation is repeated, and when the level of the digital signal of a multiplied result comes optimum, the signal Sa is recorded by a recording part 17 through a round-off circuit 47, a digital signal processing circuit 15 and a high frequency map 16.
JP16931387A 1987-07-07 1987-07-07 Digital recording device Expired - Fee Related JPH0770155B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16931387A JPH0770155B2 (en) 1987-07-07 1987-07-07 Digital recording device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16931387A JPH0770155B2 (en) 1987-07-07 1987-07-07 Digital recording device

Publications (2)

Publication Number Publication Date
JPS6413262A true JPS6413262A (en) 1989-01-18
JPH0770155B2 JPH0770155B2 (en) 1995-07-31

Family

ID=15884219

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16931387A Expired - Fee Related JPH0770155B2 (en) 1987-07-07 1987-07-07 Digital recording device

Country Status (1)

Country Link
JP (1) JPH0770155B2 (en)

Also Published As

Publication number Publication date
JPH0770155B2 (en) 1995-07-31

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