JPS6399634A - Optical reception circuit - Google Patents
Optical reception circuitInfo
- Publication number
- JPS6399634A JPS6399634A JP61244901A JP24490186A JPS6399634A JP S6399634 A JPS6399634 A JP S6399634A JP 61244901 A JP61244901 A JP 61244901A JP 24490186 A JP24490186 A JP 24490186A JP S6399634 A JPS6399634 A JP S6399634A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- voltage
- time constant
- apd
- voltage circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000003287 optical effect Effects 0.000 title claims description 9
- 230000005669 field effect Effects 0.000 claims description 8
- 230000005685 electric field effect Effects 0.000 abstract 2
- 230000005540 biological transmission Effects 0.000 abstract 1
- 230000007704 transition Effects 0.000 abstract 1
- 239000003990 capacitor Substances 0.000 description 9
- 238000001914 filtration Methods 0.000 description 8
- 230000003321 amplification Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 238000003199 nucleic acid amplification method Methods 0.000 description 4
- 230000007423 decrease Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000005684 electric field Effects 0.000 description 1
- 239000000284 extract Substances 0.000 description 1
Landscapes
- Optical Communication System (AREA)
Abstract
Description
【発明の詳細な説明】
〔概要〕
アバランシェ・フＡｌ・・ダイオード（以下Ａ ｆ）Ｄ
と略ず）を用いた先受（Ａ回１１’３において、当該Ａ
））Ｄに印加する直流電圧回路に、時定数切換機能を有
する濾波回路をもうけ、雑音による誤受信を防止すると
共に受信状態への立上りを高速化するようにしたことが
開示される。[Detailed Description of the Invention] [Summary] Avalanche Al...diode (hereinafter referred to as A f) D
(abbreviated)) (in the A inning 11'3, the A
)) It is disclosed that a filtering circuit having a time constant switching function is provided in the DC voltage circuit applied to D to prevent erroneous reception due to noise and to speed up the rise to the reception state.
本発明は、光受信回路、特にＡ ）） Ｄを用いた光受
信回路において、Ａ Ｉ） Ｉ）に印加する比較的高い
直流電圧を、受信回路の立上り時に早期に立−Ｌげかつ
通常時当該直流電圧上に重畳する非所望な雑音電圧を除
去するよう乙にし７た光受信回路に関する。The present invention provides an optical receiving circuit, particularly an optical receiving circuit using A)) D, in which a relatively high DC voltage applied to A) The present invention relates to an optical receiving circuit that removes undesired noise voltage superimposed on the DC voltage.
従来から、Ａ Ｐ Ｉ）を用いた光受信回路は、第３図
図ボの構成をそなえている。１メ１中の符ｙＪ１はＡＰ
Ｄ、２は電圧回路であ−っで例えば１８０（■）程度の
直流電圧を発生するもの、３は信号増幅回路であってＡ
ＰＤＩを流れる電流の中から交流成分を抽出して増幅す
るもの、４はコンデンサであって濾波回路を構成するも
のを表わす。Conventionally, optical receiving circuits using API have had the configuration shown in FIG. 3. The symbol yJ1 in 1me1 is AP
D, 2 is a voltage circuit, which generates a DC voltage of, for example, about 180 (■), and 3 is a signal amplification circuit, A.
4 represents a capacitor that extracts and amplifies an alternating current component from the current flowing through the PDI and constitutes a filter circuit.
また第４図は他の構成であって、図中の符合１．２．３
は第３図に対応している。Moreover, FIG. 4 shows another configuration, and the reference numerals 1.2.3 in the figure
corresponds to Fig. 3.
ＡＰＤＩを用いる光受信回路においては、比較的高い直
流電圧をＡＰＤｌに印加するようにされている。このた
めに、上記直流電圧を高精度で安定化しようとすると、
大きい容量の電圧回路２を必要とする。電圧回路２を比
較的小型のもので足りるようにするために、第３図図示
の如く、大容量のコンデンサ４を配置することが行われ
る。In an optical receiving circuit using APDI, a relatively high DC voltage is applied to APDl. For this reason, when trying to stabilize the above DC voltage with high precision,
A voltage circuit 2 with a large capacity is required. In order to make the voltage circuit 2 relatively small, a large capacity capacitor 4 is arranged as shown in FIG.
第３図図示の如き光受信回路を、光通信を用いたコール
・ハイ・コール（ｃａｌｌ ｂｙ ｃａｌｌ）給電方式
に採用しようとすると、加入者からのアクセス時間の制
約があるために、上記コンデンサ４の存在が問題となる
。即ち、コンデンサ４が上記立上り時間を遅延させるよ
うに働らいている。If an optical receiving circuit as shown in FIG. The existence of is a problem. That is, the capacitor 4 functions to delay the rise time.
この点を考慮して、第４図図示の如くコンデンサ４を省
略すると、電圧回路２の容量を大にしない限ぎり、直流
電圧にリップル分や雑音信号が重畳し、誤受信となりか
ねない。In consideration of this point, if the capacitor 4 is omitted as shown in FIG. 4, unless the capacity of the voltage circuit 2 is increased, ripples and noise signals will be superimposed on the DC voltage, which may result in erroneous reception.
本発明は、上記の点を解決しており、立上げ時に実質上
濾波機能をなくしかつ通常時に濾波機能を有効に働らか
せるようにした濾波回路をもうけ、当該濾波回路の時定
数を、電界効果トランジスタの導通抵抗を制御して切換
えるようにしている。The present invention solves the above-mentioned problems, and includes a filtering circuit that substantially eliminates the filtering function at startup and allows the filtering function to work effectively during normal times, and changes the time constant of the filtering circuit to the electric field. The switching is performed by controlling the conduction resistance of the effect transistor.
第１図は本発明の原理構成図を示す。図中の符号１はＡ
ＰＤ、２は電圧回路、３は信号増幅回路、５は時定数切
換機能を有する濾波回路、６は信号検出器、Ｃはコンデ
ンサ、ＦＩＥＴは電界効果トランジスタを表わしている
。FIG. 1 shows a basic configuration diagram of the present invention. The code 1 in the diagram is A
PD, 2 is a voltage circuit, 3 is a signal amplification circuit, 5 is a filter circuit having a time constant switching function, 6 is a signal detector, C is a capacitor, and FIET is a field effect transistor.
信号検出器６は、信号増幅回路３において抽出され増幅
される受信信号を検出するものであり、電界効果トラン
ジスタＦＥＴは信号検出器６の出力によって制御される
。The signal detector 6 detects the received signal extracted and amplified in the signal amplification circuit 3, and the field effect transistor FET is controlled by the output of the signal detector 6.
立上げ時とその直後には、信号検出器６は受信信号を検
出していない。このために信号検出器６の出力は零であ
り、電界効果トランジスタＦＥＴの導通抵抗は十分に大
である。したがって、濾波回路５の時定数は十分に大で
あり、実質上濾波回路５が存在しないものと同様に働ら
く。即ち、第４図に示す構成と同じ形となる。At startup and immediately after, the signal detector 6 does not detect a received signal. Therefore, the output of the signal detector 6 is zero, and the conduction resistance of the field effect transistor FET is sufficiently large. Therefore, the time constant of the filtering circuit 5 is sufficiently large, and it functions substantially as if the filtering circuit 5 were not present. That is, it has the same shape as the configuration shown in FIG.
この立上げが行われた後に、信号検出器６が受信信号を
検出するようになると、電界効果トランジスタＦＥＴの
導通抵抗がゆっ（りと小になるように制御される。その
結果、最終的には、濾波回路５の時定数は小となり、実
質上コンデンサＣのみが接続された形となる。After this start-up, when the signal detector 6 starts to detect the received signal, the conduction resistance of the field effect transistor FET is controlled to gradually decrease.As a result, the In this case, the time constant of the filtering circuit 5 is small, and only the capacitor C is substantially connected.
第２図は本発明の一実施例構成を示す。図中の符号１な
いし６、およびＣ，ＦＥＴは第１図に対４一
応し、７は増幅器、８は時限回路、９は抵抗、１０はコ
ンデンサ、１１はダイオードを表わしている。FIG. 2 shows the configuration of an embodiment of the present invention. Reference numerals 1 to 6 and C and FET in the figure correspond to pair 4 in FIG. 1, 7 is an amplifier, 8 is a timer circuit, 9 is a resistor, 10 is a capacitor, and 11 is a diode.
回路の基本的構成は第１図図示のものと実質上全く同じ
である。第２図図示の場合、信号検出器６の出力は増幅
器７によって増幅される。そして、増幅器７に出力が現
われるにつれて、コンデンサ１０が充電されてゆき、電
界効果トランジスタＦＥＴの導通抵抗をゆっくりと小に
してゆく。なお、ダイオード１１は、増幅器７の出力電
圧が低下した際に、コンデンサ１０の電荷を高速度で放
散させるためのものである。The basic configuration of the circuit is substantially the same as that shown in FIG. In the case shown in FIG. 2, the output of the signal detector 6 is amplified by an amplifier 7. Then, as the output appears in the amplifier 7, the capacitor 10 is charged, and the conduction resistance of the field effect transistor FET is gradually reduced. Note that the diode 11 is for dissipating the charge in the capacitor 10 at a high speed when the output voltage of the amplifier 7 decreases.
以上説明した如く、本発明によれば、電圧回路として比
較的小さい容量のもので足りるようにした上で、受信回
路の立上りを高速化しかつ雑音などの影響をなくしてい
る。このために、加入者からのアクセス時間に制約があ
るコール・パイ・コール給電方式を採用するに当って、
きわめて太きい効果を奏することができる。As explained above, according to the present invention, a relatively small capacitance voltage circuit is sufficient, and the rise of the receiving circuit is made faster and the influence of noise is eliminated. For this reason, when adopting a call-by-call power supply system that imposes restrictions on access time from subscribers,
It can produce extremely strong effects.
第１図は本発明の原理構成図、第２図は本発明の一実施
例構成を示す。
図中の符号１はＡＰＤ、２は電圧回路、３は信号増幅回
路、５は時定数切換機能をもつ濾波回路。
ＦＥＴは電界効果トランジスタを表わす。FIG. 1 shows the principle configuration of the present invention, and FIG. 2 shows the configuration of an embodiment of the present invention. In the figure, numeral 1 is an APD, 2 is a voltage circuit, 3 is a signal amplification circuit, and 5 is a filter circuit with a time constant switching function. FET stands for field effect transistor.
Claims (1)
、当該アバランシェ・フォト・ダイオードに対して電圧
を印加する電圧回路とをそなえ、当該電圧回路によって
電圧が印加されている状態の下で上記ダイオードに供給
された光を電気信号の形で受信する光受信回路において
、 上記電圧回路の出力端と上記ダイオードとの間に、時定
数切換機能を有する濾波回路をもうけ、該濾波回路内に
時定数回路の１つを構成する電界効果トランジスタがも
うけられ、該電界効果トランジスタを上記受信した信号
によって制御し、当該トランジスタの導通抵抗を変更す
るようにした ことを特徴とする光受信回路。[Claims] A light receiving circuit using an avalanche photodiode and a voltage circuit that applies a voltage to the avalanche photodiode are provided, and under a state where a voltage is applied by the voltage circuit, In the optical receiving circuit that receives the light supplied to the diode in the form of an electrical signal, a filter circuit having a time constant switching function is provided between the output terminal of the voltage circuit and the diode, and a filter circuit is provided within the filter circuit. An optical receiving circuit characterized in that a field effect transistor constituting one of the time constant circuits is provided, and the field effect transistor is controlled by the received signal to change the conduction resistance of the transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61244901A JPS6399634A (en) | 1986-10-15 | 1986-10-15 | Optical reception circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61244901A JPS6399634A (en) | 1986-10-15 | 1986-10-15 | Optical reception circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6399634A true JPS6399634A (en) | 1988-04-30 |
Family
ID=17125656
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61244901A Pending JPS6399634A (en) | 1986-10-15 | 1986-10-15 | Optical reception circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6399634A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5602670A (en) * | 1994-10-26 | 1997-02-11 | Rheem Manufacturing Company | Optical data receiver employing a solar cell resonant circuit and method for remote optical data communication |
| WO2000076093A1 (en) * | 1999-06-07 | 2000-12-14 | Fujitsu Limited | Bias circuit for photodetector, and receiver for optical communication |
| JPWO2008099507A1 (en) * | 2007-02-16 | 2010-05-27 | 富士通オプティカルコンポーネンツ株式会社 | Optical receiver |
| JP2021069025A (en) * | 2019-10-24 | 2021-04-30 | 住友電気工業株式会社 | Photoreceiver |
-
1986
- 1986-10-15 JP JP61244901A patent/JPS6399634A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5602670A (en) * | 1994-10-26 | 1997-02-11 | Rheem Manufacturing Company | Optical data receiver employing a solar cell resonant circuit and method for remote optical data communication |
| WO2000076093A1 (en) * | 1999-06-07 | 2000-12-14 | Fujitsu Limited | Bias circuit for photodetector, and receiver for optical communication |
| US6707024B2 (en) | 1999-06-07 | 2004-03-16 | Fujitsu Limited | Bias circuit for a photodetector, and an optical receiver |
| JPWO2008099507A1 (en) * | 2007-02-16 | 2010-05-27 | 富士通オプティカルコンポーネンツ株式会社 | Optical receiver |
| JP4998478B2 (en) * | 2007-02-16 | 2012-08-15 | 富士通オプティカルコンポーネンツ株式会社 | Optical receiver |
| US8306437B2 (en) | 2007-02-16 | 2012-11-06 | Fujitsu Limited | Optical receiver |
| JP2021069025A (en) * | 2019-10-24 | 2021-04-30 | 住友電気工業株式会社 | Photoreceiver |
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