JPS6399594A - Manufacture of printed wiring board - Google Patents
Manufacture of printed wiring boardInfo
- Publication number
- JPS6399594A JPS6399594A JP24497986A JP24497986A JPS6399594A JP S6399594 A JPS6399594 A JP S6399594A JP 24497986 A JP24497986 A JP 24497986A JP 24497986 A JP24497986 A JP 24497986A JP S6399594 A JPS6399594 A JP S6399594A
- Authority
- JP
- Japan
- Prior art keywords
- solder resist
- printed wiring
- wiring board
- conductor layer
- printing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 229910000679 solder Inorganic materials 0.000 claims description 40
- 238000000034 method Methods 0.000 claims description 20
- 239000004020 conductor Substances 0.000 claims description 18
- 238000007639 printing Methods 0.000 claims description 12
- 238000005476 soldering Methods 0.000 claims description 9
- 239000000758 substrate Substances 0.000 claims description 5
- 238000005498 polishing Methods 0.000 claims description 3
- 238000010019 resist printing Methods 0.000 description 6
- 230000000740 bleeding effect Effects 0.000 description 5
- 230000000694 effects Effects 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
Landscapes
- Non-Metallic Protective Coatings For Printed Circuits (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はプリント配線基板の製造方法に関するものであ
り、特にチップ部品実装用プリント配線基板のソルダー
レジスト印刷技術に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a printed wiring board, and particularly to a solder resist printing technique for a printed wiring board for mounting chip components.
本発明はプリント配線基板の製造方法において、配線回
路パターンとは逆のパターンを有するマスクを用いて基
板上に第１のソルダーレジスト印刷を行った後、導体層
の表面を研摩し、次いで、導体層のうちのハンダ付領域
を除いた部分に対応したパターンを有するマスクを用い
て導体層上に第２のソルダーレジスト印刷を行うように
することにより、
ソルダーレジストの「ニジミ」 （ハンダ付領域への印
刷滲み）、「エツジ入らす」 （非ハンダ付領域の露出
）及びチップ部品実装時の半田未着の問題を同時に解決
することができるようにしたものである。The present invention relates to a method for manufacturing a printed wiring board, in which a first solder resist is printed on the board using a mask having a pattern opposite to that of the printed circuit pattern, the surface of the conductor layer is polished, and then the conductor layer is By printing a second solder resist on the conductor layer using a mask with a pattern corresponding to the part of the layer excluding the soldering area, solder resist "bleeding" (into the soldering area) can be avoided. It is possible to simultaneously solve the problems of print smearing), "edge penetration" (exposure of non-soldered areas), and non-solder adhesion during chip component mounting.
従来より、例えばテレビジョン受像機、ラジオ受信機等
の電子機器にはプリント配線基板が多用されている。こ
のプリント配線基板は、例えば、絶縁基板上に導体材料
により配線回路パターンを形成した後、いわゆるハンダ
ブリッジ等を防止するために、ランド（ハンダ付領域）
を除く領域すなわちランド間を接続するラインを含む非
ハンダ付領域にソルダーレジストを塗布することによっ
て製造される。又、従来このプリント配線基板にチップ
部品を半田デイツプ法などで固着させることが行われて
いる。この場合、ソルダーレジストを塗布してからチッ
プ部品の半田付けを行う。ソルダーレジストの塗布は通
常スクリーン印刷により行われる。その際に、非ハンダ
付領域にソルダーレジストを１回だけ印刷する従来の印
刷方法（１回印刷法）には「ニジミ」及び「エツジ入ら
ず」の問題があった。そこでこの問題を解決するために
、基板上の非ハンダ付領域を完全に被覆するようにかつ
導体層の厚み以上の厚みをもって第１のソルダーレジス
ト印刷を行った後、導体層上を研摩し、ハンダ付領域以
外の領域に第２のソルダーレジスト印刷を行う２回印刷
法が提案されてい配線基板においてチップ実装が増加し
、上記２回印刷法を行ったプリント配線基板でチップ実
装時に半田未着の問題か新たに発生している。Conventionally, printed wiring boards have been widely used in electronic devices such as television receivers and radio receivers. For example, in this printed wiring board, after a wiring circuit pattern is formed using a conductive material on an insulating substrate, a land (soldering area) is formed in order to prevent so-called solder bridges.
It is manufactured by applying a solder resist to the non-soldered area including the line connecting between the lands. Furthermore, conventionally, chip components have been fixed to this printed wiring board by a solder dip method or the like. In this case, the chip components are soldered after applying the solder resist. Application of solder resist is usually performed by screen printing. At that time, the conventional printing method (single printing method) in which the solder resist is printed only once on the non-soldered area has the problem of "bleeding" and "no edges". Therefore, in order to solve this problem, after printing the first solder resist so as to completely cover the non-soldered area on the board and with a thickness greater than the thickness of the conductor layer, the conductor layer is polished. A two-time printing method has been proposed in which a second solder resist is printed in areas other than the soldering area.The number of chips mounted on wiring boards has increased, and solder does not adhere when chips are mounted on printed wiring boards that have been subjected to the two-time printing method. A new problem has occurred.
そこで、本発明は従来の１回印刷法における「ニジミ」
及び「エツジ入らず」の問題を解決すると同時に半田未
着の問題を解決することを目的とする。Therefore, the present invention solves the problem of "bleeding" in the conventional one-time printing method.
The purpose of the present invention is to solve the problem of "edges not entering" and at the same time solve the problem of solder not adhering.
本発明者らは上記の問題点を解決するために鋭意検討し
た結果、本発明に到達した。The present inventors have made extensive studies to solve the above problems, and as a result, have arrived at the present invention.
即ち、本発明は、絶縁基板上に配線回路パターンの導体
層を有するプリント配線基板の製造方法において、前記
パターンとは逆のパターンを有するマスクを用いて基板
上に第１のソルダーレジスト印刷を行った後、前記導体
層の表面を機械的に研摩し、次いで、前記導体層のうち
のハンダ付領域を除いた部分に対応するパターンを有す
るマスクを用いて導体層上に第２のソルダーレジスト印
刷を行うプリント配線基板の製造方法に係る。That is, the present invention provides a method for manufacturing a printed wiring board having a conductor layer with a wiring circuit pattern on an insulating substrate, which includes printing a first solder resist on the substrate using a mask having a pattern opposite to the above pattern. After that, the surface of the conductor layer is mechanically polished, and then a second solder resist is printed on the conductor layer using a mask having a pattern corresponding to a portion of the conductor layer excluding the soldering area. The present invention relates to a method for manufacturing a printed wiring board.
本発明によれば、第１のソルダーレジスト印刷後の機械
的研摩によって、ソルダーレジストを塗布する必要のな
いハンダ付領域に滲み出したソルダーレジストが除去さ
れ、第２のソルダーレジスト印刷では導体層のうちのハ
ンダ付領域を除いた部分にのみソルダーレジストを印刷
するようにしているため、先に提案された２回印刷法に
比べてチップ部品を実装した場合のチップ部品とソルダ
ーレジストとの間隙を大きくすることができ、半田未着
の問題が解決され、同時に「ニジミ」及び「エツジ入ら
ず」といった従来の１回印刷法の問題点も効果的に解決
される。According to the present invention, mechanical polishing after the first solder resist printing removes the solder resist that has oozed out into the soldering areas where it is not necessary to apply the solder resist, and the second solder resist printing removes the solder resist that has oozed out into the soldering area where the solder resist does not need to be applied. Since the solder resist is printed only on the part excluding the soldering area, the gap between the chip component and the solder resist when the chip component is mounted is reduced compared to the previously proposed two-time printing method. This solves the problem of non-solder adhesion, and at the same time effectively solves the problems of the conventional one-time printing method, such as "bleeding" and "no edges".
以下、本発明のプリント配線基板の製造方法の一実施例
を図面に沿って工程順に説明する。なお、本実施例にお
けるプリント配線基板は両面基板であるが、説明を簡略
化するために一方の面についてのみ説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the method for manufacturing a printed wiring board according to the present invention will be described below in the order of steps with reference to the drawings. Although the printed wiring board in this embodiment is a double-sided board, only one side will be described to simplify the explanation.
先ず、絶縁基板１上にランド２、ライン３．４等からな
る配線回路パターンの銅導体層を有し、スルホール５が
形成された第１図のプリント配線基板に回路パターンと
は逆のパターンを有するマスクを用いて導体層の厚さよ
り薄く第１のソルダーレジスト６を印刷する（第２図）
。なお、この工程において、ソルダーレジスト６がラン
ド２の端部領域２ａに掛かっても、これは次の工程で除
去されるため差し支えない。First, a copper conductor layer with a wiring circuit pattern consisting of lands 2, lines 3, 4, etc. is formed on an insulating substrate 1, and a pattern opposite to the circuit pattern is formed on the printed wiring board shown in FIG. 1 in which through holes 5 are formed. Print the first solder resist 6 thinner than the thickness of the conductor layer using a mask (Figure 2).
. Note that in this step, even if the solder resist 6 covers the end region 2a of the land 2, there is no problem since this will be removed in the next step.
次に、ソルダーレジスト６を乾燥しランド２及びライン
３．４等からなる導体層の表面を機械的に研摩して導体
層上のソルダーレジストを除去する（第３図）。上記研
摩は、例えば、回転ベルト式研摩機を用いて行えばよい
。Next, the solder resist 6 is dried and the surface of the conductor layer consisting of the lands 2, lines 3, 4, etc. is mechanically polished to remove the solder resist on the conductor layer (FIG. 3). The above polishing may be performed using, for example, a rotating belt type polisher.
最後に、ライン３．４に対応する部分に開口を有するマ
スクを用いて、ライン３．４に第２のソルダーレジスト
マをスクリーン印刷する。第１のソルダーレジスト印刷
の際に発生することがあるエツジ入らずば、この第２の
ソルダーレジスト印刷によって解消することができる。Finally, a second solder resist is screen printed on line 3.4 using a mask having an opening in a portion corresponding to line 3.4. Edges that may occur during the first solder resist printing can be eliminated by this second solder resist printing.
次いで、こうして本実施例の方法により得られたプリン
ト配線基板上にチップ部品８を接着剤９により仮接着す
る（第５図）。次いでチップ部品８は半田デイツプ法に
より固着される。第５図から明らかなように、このプリ
ント配＆ｉｌ基板においては、チップ部品とソルダーレ
ジストとの間隙が大きく、ガスが早く抜けるため、チッ
プ実装時の半田未着の発生を効果的に回避できる。Next, a chip component 8 is temporarily bonded onto the printed wiring board obtained by the method of this embodiment using an adhesive 9 (FIG. 5). Next, the chip component 8 is fixed by a solder dip method. As is clear from FIG. 5, in this printed wiring board, the gap between the chip component and the solder resist is large, and gas can escape quickly, so that it is possible to effectively avoid the occurrence of unsolder adhesion during chip mounting.
本発明はプリント配線基板の製造方法が上述の様な構成
を有するようにしているため、１、従来のソルダーレジ
スト１回印刷法において発生したソルダーレジストの「
ニジミ」や「エツジ入らずｊ等の印刷不良を効果的に回
避でき、従来のソルダーレジスト１回印刷法に比ベプリ
ント配線基板の製造歩留りが向上する、２、チップ部品
実装時の半田未着の問題を効果的に解決し、かつソルダ
ーレジストの使用量を減少させることができる、
３、ホトプロセスによる製造方法に比ベコストが安くな
る、
等の利点を有する。In the present invention, since the method for manufacturing a printed wiring board has the above-described configuration, 1.
It can effectively avoid printing defects such as "bleeding" and "missing edges", and improve the manufacturing yield of printed wiring boards compared to the conventional one-time solder resist printing method.2. It has the following advantages: it can effectively solve the problem and reduce the amount of solder resist used; 3. It is cheaper than the photoprocess manufacturing method.
第１図〜第４図は本発明の方法の一実施例を工程順に示
すプリント配線基板の概略断面図、第５図は前記実施例
により得られ更にチップ部品を仮接着したプリント配線
基板の概略断面図である。
なお図面に用いた符号において、
１−−−−−−−−−−−−−−−！＠縁基板２−−−
−−−−−−−−−−・−・ランド３．４−・−−−一
−−−−ライン
６．７−−−−−−−−−−ソルダーレジストである。1 to 4 are schematic cross-sectional views of a printed wiring board showing an example of the method of the present invention in the order of steps, and FIG. 5 is a schematic sectional view of a printed wiring board obtained by the above example and further having chip components temporarily bonded. FIG. In addition, in the symbols used in the drawings, 1----------! @Edge board 2---
------------Land 3.4--Line 6.7--Solder resist.
Claims (1)
ント配線基板の製造方法において、前記パターンとは逆
のパターンを有するマスクを用いて基板上に第１のソル
ダーレジスト印刷を行った後、前記導体層の表面を機械
的に研摩し、次いで、前記導体層のうちのハンダ付領域
を除いた部分に対応したパターンを有するマスクを用い
て導体層上に第２のソルダーレジスト印刷を行うプリン
ト配線基板の製造方法。In a method for manufacturing a printed wiring board having a conductor layer having a wiring circuit pattern on an insulating substrate, a first solder resist is printed on the board using a mask having a pattern opposite to the pattern, and then the conductor layer is mechanically polishing the surface of the printed wiring board, and then printing a second solder resist on the conductor layer using a mask having a pattern corresponding to the portion of the conductor layer excluding the soldering area. Production method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24497986A JPS6399594A (en) | 1986-10-15 | 1986-10-15 | Manufacture of printed wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24497986A JPS6399594A (en) | 1986-10-15 | 1986-10-15 | Manufacture of printed wiring board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6399594A true JPS6399594A (en) | 1988-04-30 |
Family
ID=17126788
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP24497986A Pending JPS6399594A (en) | 1986-10-15 | 1986-10-15 | Manufacture of printed wiring board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6399594A (en) |
-
1986
- 1986-10-15 JP JP24497986A patent/JPS6399594A/en active Pending
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