JPS639958A - Semiconductor microwave circuit element - Google Patents
Semiconductor microwave circuit elementInfo
- Publication number
- JPS639958A JPS639958A JP61152679A JP15267986A JPS639958A JP S639958 A JPS639958 A JP S639958A JP 61152679 A JP61152679 A JP 61152679A JP 15267986 A JP15267986 A JP 15267986A JP S639958 A JPS639958 A JP S639958A
- Authority
- JP
- Japan
- Prior art keywords
- lower layer
- oxide film
- layer
- silicon oxide
- photosensor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 20
- 238000009413 insulation Methods 0.000 claims abstract description 8
- 239000010408 film Substances 0.000 claims description 51
- 239000010410 layer Substances 0.000 claims description 26
- 230000003287 optical effect Effects 0.000 claims description 14
- 239000010409 thin film Substances 0.000 claims description 5
- 239000011229 interlayer Substances 0.000 claims description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 27
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 27
- 239000000969 carrier Substances 0.000 abstract description 5
- 238000006243 chemical reaction Methods 0.000 abstract description 5
- 230000035945 sensitivity Effects 0.000 abstract description 5
- 230000006866 deterioration Effects 0.000 abstract description 3
- 235000010627 Phaseolus vulgaris Nutrition 0.000 abstract 1
- 244000046052 Phaseolus vulgaris Species 0.000 abstract 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 19
- 229910052710 silicon Inorganic materials 0.000 description 19
- 239000010703 silicon Substances 0.000 description 19
- 239000000758 substrate Substances 0.000 description 8
- 238000005530 etching Methods 0.000 description 5
- 238000002347 injection Methods 0.000 description 5
- 239000007924 injection Substances 0.000 description 5
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 2
- 239000002344 surface layer Substances 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 230000031700 light absorption Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000001953 recrystallisation Methods 0.000 description 1
- 238000002834 transmittance Methods 0.000 description 1
Landscapes
- Solid State Image Pick-Up Elements (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分前〕
この発明は、半導体薄膜および絶縁膜が順次積層されて
形成され、少なくとも最上層に光センサデバイスを有す
る複数のデバイスの積層構造の半導体立体回路素子に関
する。Detailed Description of the Invention [Before Industrial Use] The present invention provides a semiconductor three-dimensional device having a stacked structure of a plurality of devices, which is formed by sequentially stacking semiconductor thin films and insulating films, and has a photosensor device in at least the top layer. Regarding circuit elements.
一般に、半導体薄膜および絶縁膜を順次積層し、各層の
半導体薄膜に信号処理回路や記憶回路などの種々のデバ
イスを形成した積層構造の半導体立体回路素子を作成し
、回路の高密度化、高集積化を図ることが行なわれてい
る。In general, semiconductor three-dimensional circuit elements with a stacked structure are created by sequentially stacking semiconductor thin films and insulating films, and various devices such as signal processing circuits and memory circuits are formed on each layer of semiconductor thin films. Efforts are being made to make this happen.
そして、このような半導体立体回路素子として、たとえ
ば１９８５シンポジウムオンＶＬＳ Ｉチクノロシイ、
ダイジェスト頁２８〜２９ ＩＶ−５Ｃ１９８５Ｓｙｍ
ｐｏｓｉｕｍ ｏｎ ＶＬＳＩ Ｔｅｃｈｎｏｌｏｇｙ
、 Ｄｙｇｅｓｔ Ｐ。As such semiconductor three-dimensional circuit elements, for example, the 1985 Symposium on VLS I Technology,
Digest pages 28-29 IV-5C1985Sym
Posium on VLSI Technology
, Digest P.
２８〜２９ ＩＶ−５１あるいは１９８５シンポジウム
オンＶＬＳＩチクノロシイ、ダイジェスト頁３４〜３５
■Ｖ−Ｂ （： １ ｇＢ５ Ｓｙｍｐｏｓｉｕｍ ｏ
ｎ ＶＬＳ Ｉ Ｔｅｃｈｎｏｌｏｇｙ 。28-29 IV-51 or 1985 Symposium on VLSI Technology, Digest pages 34-35
■V-B (: 1 gB5 Symposium o
n VLS I Technology.
Ｄｉｇｅｓｔ Ｐ、 ３４〜３５ ＩＶ−８３に記載の
ように、最上層に光電変換機能を・有する光センサデバ
イスを形成したイメージプロセッサの開発が行なわれて
おり、この種の半導体立体回路素子はたとえば第５図に
示すように構成されている。As described in Digest P, 34-35 IV-83, an image processor in which a photosensor device having a photoelectric conversion function is formed in the top layer has been developed, and this type of semiconductor three-dimensional circuit element is, for example, It is configured as shown in Figure 5.
すなわち、第５図において、（１）は単結晶シリコン基
板、（２） 、 （３）は基板（１）の表面に不純物の
拡散により形成された基板（１）と反対の導電型のソー
ス領域オヨヒトレイン領域、（４）ｊ（５）、（６）は
ＣＶＤ法により基板（１）上に形成されたゲート電極、
ソース電極およびドレイン電極、（７）は基板（１）の
両端表層部にそれぞれ形成されたフィールド絶縁用のシ
リコン酸化膜、（８）は基板（１）、ソース、ドレイン
領域（２）。That is, in FIG. 5, (1) is a single crystal silicon substrate, (2) and (3) are source regions of the opposite conductivity type to that of the substrate (1), which are formed on the surface of the substrate (1) by diffusion of impurities. Oyohito train region, (4)j (5), (6) are gate electrodes formed on the substrate (1) by CVD method,
A source electrode and a drain electrode, (7) a silicon oxide film for field insulation formed on the surface layer of both ends of the substrate (1), and (8) a source and drain region (2) of the substrate (1).
（３）、各電極（４）〜（６）、シリコン酸化膜（７）
により構成された信号処理回路等の下層デバイス、（９
）はＣＶＤ法により基板（１）、各電極（４）〜（６）
、酸化膜（７）上に形予稿集（１９８４年）２頁２０７
〜２２２に記載のように、多結晶シリコン等からなる平
坦化ヒートシンクは、積層構造の立体回路素子を再結晶
化法により作成する上で、上層の再結晶化層の結晶性を
改善し、下層のデバイスへの熱的影響を抑制するのに極
−”ｔさらに、α０はＣＶＤ法により多結晶シリコン膜
αＯ上に形成されたＳＯＩ用のシリコン酸化膜、＠はシ
リコン酸化膜αυの表層部に形成された膜厚的１μｍの
多結晶シリコン膜がレーザ再結晶化法により単結晶化さ
れて形成された単結晶シリコン島、α１゜α４）ｉ、ｔ
それぞれシリコン島（６）の表面にイオン注入により形
成されたシリコン島（２）と反対の導電型のイオン注入
層、αυはＣＶＤ法によりシリコン島＠上に形成された
多結晶シリコンからなるゲート電極、αＱはシリコン酸
化膜０１）、シリコン島（イ）およびゲート電極αυ上
に形成された絶縁用のシリコン酸化膜、α力、（至）は
それぞれシリコン島（２）および注入層α→に接触して
形成されたアルミニウムからなる信号取出用電極であり
、シリコン酸化膜０Ｑに形成された２個のコンタクトホ
ール００の内面、および注入層（至）の上側を除くシリ
コン酸化膜αＱ上に形成され、シリコン島（２）１両注
入層α３．Ｑ→、各電極αＧ、αつ、（ト）、シリコン
酸化膜ａ・により光センサデバイス（１）が構成されて
いる。(3), each electrode (4) to (6), silicon oxide film (7)
Lower layer devices such as signal processing circuits configured by (9
) is the substrate (1) and each electrode (4) to (6) by CVD method.
, Proceedings of Form on Oxide Film (7) (1984), p. 2, 207
As described in 222, a flattened heat sink made of polycrystalline silicon or the like is used to improve the crystallinity of the upper recrystallized layer and improve the Further, α0 is a silicon oxide film for SOI formed on the polycrystalline silicon film αO by the CVD method, and @ is a silicon oxide film formed on the surface layer of the silicon oxide film αυ. A single-crystal silicon island formed by single-crystallizing the polycrystalline silicon film with a thickness of 1 μm using a laser recrystallization method, α1° α4) i, t
An ion-implanted layer of the opposite conductivity type to the silicon island (2) is formed on the surface of the silicon island (6) by ion implantation, and αυ is a gate electrode made of polycrystalline silicon formed on the silicon island by the CVD method. , αQ is the silicon oxide film 01), the insulating silicon oxide film formed on the silicon island (A) and the gate electrode αυ, α force, (to) is in contact with the silicon island (2) and the injection layer α→, respectively. It is a signal extraction electrode made of aluminum and formed on the silicon oxide film αQ except for the inner surfaces of the two contact holes 00 formed in the silicon oxide film 0Q and the upper side of the injection layer (to). , silicon island (2) 1 both injection layers α3. Q→, each electrode αG, α, (g), and a silicon oxide film a constitute an optical sensor device (1).
そして、第５図中の１点鎖線矢印に示すように注入層α
埠の上側の入射面から光が入射すると、光センサデバイ
ス（４）のシリコン島（２）において光が吸収され、光
電変換部であるシリコン島（６）と注入層αｊとの接合
部近辺において、吸収された光のエネルギによるキャリ
アが生成されて電気信号が出力され出力された電気信号
が下層デバイス（８）により処理されることになる。Then, as shown by the dashed-dotted line arrow in FIG.
When light enters from the entrance surface on the upper side of the wharf, the light is absorbed by the silicon island (2) of the optical sensor device (4), and is absorbed near the junction between the silicon island (6), which is the photoelectric conversion part, and the injection layer αj. , carriers are generated by the absorbed light energy and an electrical signal is output, and the output electrical signal is processed by the lower layer device (8).
ところで、前記したシリコン島＠と同様に、厚さ１μｍ
の単結晶シリコン膜の光の吸収率を調べたところ、波長
４５０１ｍの短波長光に対する吸収率は約８９％、波長
７００ｎｔｎの長波長光に対する吸収率は約１６％とな
り、従って波長４５０〜７００ｎｍの範囲の光の透過率
は約ｉｔ〜８４％となり、とくに赤色近傍の波長の光の
ほとんどがシリコン膜を透過することになるため、第５
図の半導体立体回路素子の場合、７００ ｎｍ前後の長
波長の光に対する光センサデバイス（イ）の感度が低く
なるとともに、光センサデバイス翰のシリコン島（２）
を吸収されずに透過した光が下層デバイス（８）に入射
し、下層デバイス（８）に光干渉などの悪影響を及ぼし
て動作特性の低下を招くシ１す、ヵ、っ下層。ア７、イ
ユ。透過光９３よう動作特性の低下の防止を図ることを
技術的課題とする。By the way, like the silicon island described above, the thickness is 1 μm.
When we investigated the light absorption rate of the single crystal silicon film of The transmittance of light in the range is approximately 84%, and most of the light with wavelengths near red in particular passes through the silicon film.
In the case of the semiconductor three-dimensional circuit element shown in the figure, the sensitivity of the optical sensor device (a) to light with a long wavelength of around 700 nm becomes low, and the silicon island (2) of the optical sensor device
The light that is transmitted without being absorbed enters the lower layer device (8) and has an adverse effect on the lower layer device (8) such as optical interference, causing deterioration of the operating characteristics. A7, Iyu. The technical problem is to prevent the operating characteristics from deteriorating due to transmitted light 93.
この発明は、前記の点に留意してなされたものであり、
半導体薄膜および絶縁膜が順次積層されて形成され、少
なくとも最上層に光センサデバイスを有する複数のデバ
イスの積層構造の半導体立体回路素子において、前記光
センサデバイスと下層のデバイスとの間の層間絶縁用の
絶縁膜表面に、複数の傾斜面を有する複数の凸状部を形
成し、前記各傾斜面を、該傾斜面と隣接する前記凸状部
の傾斜面とにより入射光を入射光の入射面側ｌζ反射す
る傾斜面としたことを特徴とする半導体立体回路素子で
ある。This invention was made with the above points in mind,
In a semiconductor three-dimensional circuit element having a stacked structure of a plurality of devices in which a semiconductor thin film and an insulating film are sequentially laminated and has a photosensor device in at least the top layer, for interlayer insulation between the photosensor device and a lower layer device. A plurality of convex portions having a plurality of sloped surfaces are formed on the surface of the insulating film, and each of the sloped surfaces is connected to the sloped surface of the convex portion adjacent to the insulating film so that the incident light is converted into an incident surface of the incident light. This is a semiconductor three-dimensional circuit element characterized by having an inclined surface that reflects side lζ.
したがって、この発明によると、光センサデバイスと下
、１のデバイスとの間の層間絶縁用の絶縁膜表面に複数
の傾斜面を有する複数の凸状部を形成したため、光セン
サデバイスの上側からの入射光が光センサデバイスを透
過して前記絶縁膜に達した場合に、光センサデバイスの
下側に位ｔするて下層のデバイスに達する光が大幅に低
減され、透過光による下層のデバイスの動作特性の低下
が防止されることになる。Therefore, according to the present invention, since a plurality of convex portions having a plurality of inclined surfaces are formed on the surface of the insulating film for interlayer insulation between the optical sensor device and the lower device, When incident light passes through the optical sensor device and reaches the insulating film, the light reaching the lower layer device is significantly reduced due to the position below the optical sensor device, and the lower layer device operates due to the transmitted light. This will prevent deterioration of characteristics.
さらに、前記したように、光センサデバイスを透過して
前記絶縁膜に達した入射光が、各凸状部の各傾斜面と、
隣接する凸状部の傾斜面とにより入射面側に反射される
ため、光センサデバイスで吸収されない光は光センサデ
バイスを２度通過することになり、光センサデバイスに
おいて生成されるキャリアが増大して光電変換が促進さ
れ、光センサデバイスの感度が向上する。Furthermore, as described above, the incident light that has passed through the optical sensor device and reached the insulating film is directed to each inclined surface of each convex portion.
Since the light is reflected toward the incident surface by the inclined surface of the adjacent convex portion, the light that is not absorbed by the photosensor device passes through the photosensor device twice, increasing the number of carriers generated in the photosensor device. This facilitates photoelectric conversion and improves the sensitivity of the optical sensor device.
つぎに、■実施例を示した第１図ないし第４図とともに
詳細に説明する。Next, (2) a detailed explanation will be given with reference to FIGS. 1 to 4 showing embodiments.
第１図において、第５図と同一記号は同一のものもしく
は対応するものを示し、第５図と異なる点は、光センサ
デバイス（１）と下層デバイス（８）との間の眉間絶縁
膜としてのシリコン酸化膜（９）の表面に、傾斜角４５
の複数の傾斜面Ｑ１）を有する断面がほぼ直角二等辺三
角形の複数の凸状部（イ）を形成しつぎに、第１図に示
す半導体立体回路素子であるイメージプロセッサの製造
手順について説明する。In Fig. 1, the same symbols as in Fig. 5 indicate the same or corresponding items, and the difference from Fig. 5 is that the glabellar insulation film between the optical sensor device (1) and the lower layer device (8) is The surface of the silicon oxide film (9) has an inclination angle of 45
Next, the manufacturing procedure of the image processor, which is a semiconductor three-dimensional circuit element shown in FIG. 1, will be explained. .
まず、第２図（ａ）に示すように、前記した第４図の場
合と同様にして、単結晶シリコン基板（１）の表面にソ
ース、ドレイン領域（２） Ｍ （３）を形成し、各電
極（４）〜（６）およびフィールド絶縁用のシリコン酸
化膜（７）を形成して下層デバイス（８）を作成したの
ち、層間絶縁膜としてのシリコン酸化膜（９）を積層し
、シリコン酸化膜（９）の表面を等速エツチングにより
平坦化し、その後、第２図中）に示すように、平坦化し
たシリコン酸化膜（９）上にレジスト膜（財）を塗布し
、レジスト幅が０．８μｍ、開口幅が０．２μｍとなる
ようにレジスト膜＠をパターニングし、真空度１５０ｍ
Ｔｏｒｒの真空中において、ＣＨＦ ａおよびｏ２のガ
ス流量をそれぞれ４ Ｑ ｃｃ ／ｍｉ ｎ 、 ３５
ｃｃ ／ｍｉｎとし、１３．５６ＭＨｚの高周波の出力
を１５０Ｗとするエツチング条件のもとで、シリコン酸
化膜（９）の表面を反応性イオンエツチング法（ＲＩＥ
法）によりエツチングし、第２図（Ｃ）に示すように、
シリコン酸化膜（９）の表面に複数の凸状部（財）を形
成する。First, as shown in FIG. 2(a), source and drain regions (2) M (3) are formed on the surface of a single crystal silicon substrate (1) in the same manner as in the case of FIG. 4 described above. After forming each electrode (4) to (6) and a silicon oxide film (7) for field insulation to create a lower layer device (8), a silicon oxide film (9) as an interlayer insulation film is laminated, and silicon The surface of the oxide film (9) is flattened by uniform etching, and then, as shown in Fig. 2, a resist film is coated on the flattened silicon oxide film (9), and the resist width is The resist film was patterned so that the opening width was 0.8 μm and the opening width was 0.2 μm, and the vacuum was 150 m.
In a vacuum of Torr, the gas flow rates of CHFa and O2 were 4 Q cc /min and 35
The surface of the silicon oxide film (9) was subjected to reactive ion etching (RIE) under etching conditions of cc/min and a high frequency output of 150 W at 13.56 MHz.
As shown in Figure 2 (C),
A plurality of convex portions are formed on the surface of the silicon oxide film (9).
このとき、電子通信学会技術研究報告、Ｖｏｌ。At this time, IEICE Technical Research Report, Vol.
８５ 、Ｎｏ、１１０（１９８５年）頁２１〜２６ 、
５ＳＤ８５−４５に記載されているように、レジスト膜
翰の等方性エツチング成分によるシリコン酸化膜（９）
の横方向すなわち第３図中の１点鎖線矢印方向へのエツ
チング成分Ｅ几と、シリコン酸化膜（９）自体の異方性
エラことにより、シリコン酸化膜（９）にテーパが形成
さ分により角θを制御できることになる。85, No. 110 (1985) pp. 21-26,
As described in 5SD85-45, the silicon oxide film (9) is formed by the isotropic etching component of the resist film.
A taper is formed in the silicon oxide film (9) due to the etching component E in the lateral direction, that is, in the direction of the dashed dotted line arrow in FIG. This means that the angle θ can be controlled.
さらに、このようにしてシリコン酸化膜（９）の表面に
複数の凸状部（財）を形成したのち、第２図（ｄ）に示
すように、シリコン酸化膜（９）上に多結晶シリコン膜
α０を形成し、シリコン膜００の表面を等速エツチング
により平坦化し、その後前記した第５図の場合と同様に
して、シリコン膜α０上にシリコン酸化膜αυを形成す
るとともに、シリコン酸化膜０１）の表層部に多結晶シ
リコン膜のレーザ再結晶化法による単結晶シリコン島（
２）を形成し、シリコン島（イ）の４表面に注入層α１
．α少を形成し、各電極α＄ 、 Ｑ７） 。Furthermore, after forming a plurality of convex portions on the surface of the silicon oxide film (9) in this way, polycrystalline silicon is formed on the silicon oxide film (9) as shown in FIG. A film α0 is formed, the surface of the silicon film 00 is flattened by uniform etching, and then a silicon oxide film αυ is formed on the silicon film α0 in the same manner as in the case of FIG. A single-crystal silicon island (
2), and an injection layer α1 is formed on the four surfaces of the silicon island (A).
．． Form each electrode α$, Q7).
α綽および絶縁用のシリコン酸化膜αＱを形成して光セ
ンサデバイス翰を作成し、半導体立体回路素子としての
イメージプロセッサを製造する。An optical sensor device is fabricated by forming an α frame and an insulating silicon oxide film αQ, and an image processor as a semiconductor three-dimensional circuit element is manufactured.
なお、凸状部（イ）の形成の際、レジスト膜（イ）間に
開口を形成する必要があるため、各凸状部（イ）間のそ
して、第１図中の１点鎖線矢印に示すように一一収され
、シリコン島（６）と注入層別の接合部近辺において、
吸収された光のエネルギによるキャリアが生成されて電
気信号が出力され、下層デバイス（８）により信号処理
が行なわれる。In addition, when forming the convex portions (A), it is necessary to form an opening between the resist films (A), so between each convex portion (A) and at the dashed-dotted line arrow in FIG. As shown, in the vicinity of the junction between the silicon island (6) and the implanted layer,
Carriers are generated by the energy of the absorbed light and an electrical signal is output, and the signal is processed by the lower layer device (8).
一方、シリコン島（６）を吸収されず透過してシリコン
酸化膜（９）に達した光は、第４図に示すように、凸状
部（イ）の傾斜面ぐ→により横方向へ直角に反射されて
隣接する凸状部（イ）の傾斜面Ｃ２１）に入射し、当該
傾斜面■ηによりさらに上方へ直角に反射されることに
なり、各凸状部（イ）により、シリコン島（２）を透過
した光は入射面側に反射され、シリコン島＠を２度通過
することになり、光センサデバイス（１）により生成さ
れるキャリアが従来に比べて増大し、光電変換が効率よ
く行なわれ、たとえば波長４５０ｎｍ 、 ６００ｎｍ
、 ７００ｎｍの光を入射したときの素子の量子効率
を測定した結果、それぞれ７１％、４８％。On the other hand, as shown in Figure 4, the light that passes through the silicon island (6) without being absorbed and reaches the silicon oxide film (9) is oriented horizontally at right angles due to the inclined surface of the convex portion (A). It is reflected onto the slope C21) of the adjacent convex part (A), and is further reflected upward at right angles by the slope ■η, and each convex part (A) makes the silicon island The light that has passed through (2) is reflected to the incident surface side and passes through the silicon island twice, which increases the number of carriers generated by the optical sensor device (1) compared to the conventional method, making photoelectric conversion more efficient. This is often done, for example, at wavelengths of 450 nm and 600 nm.
The quantum efficiency of the device when 700 nm light was incident was 71% and 48%, respectively.
２７％となり、第５図に示す従来の素子に対する同人射
した光は、第４図中の２点鎖線矢印に示すように、一部
反射し、残りはシリコン酸化膜（９）を透過して下層デ
バイス（８）に達するが、全体的に見て、下層デバイス
（８）に達する光の１は、当該平坦部の面積と凸状部（
イ）の水平投影面の面積との比により、シリコン酸化膜
（９）に達した光の量の約１１５にしかならず、従来の
ように凸状部（イ）のない場合に比べて下層デバイス（
８）に与える光干渉などの悪影響が大幅に低減されるこ
とになり、その結果下層デバイス（８）が誤動作しない
ための素子への入射光の許容強度は従来のおよそ２倍に
まで増大させることが可能となる。27%, and the light incident on the conventional element shown in Figure 5 is partially reflected, as shown by the two-dot chain arrow in Figure 4, and the rest is transmitted through the silicon oxide film (9). Overall, the amount of light reaching the lower layer device (8) is determined by the area of the flat part and the convex part (
The amount of light reaching the silicon oxide film (9) is only about 115% due to the ratio of the area of the horizontal projection plane (a) to the area of the horizontal projection plane, which is compared to the conventional case without the convex part (a).
8) will be significantly reduced, and as a result, the allowable intensity of light incident on the element to prevent the lower layer device (8) from malfunctioning will be increased to about twice that of the conventional one. becomes possible.
なお、傾斜面２１）の傾斜角は前記した４５に限るもの
ではなく、傾斜面Ｑυへの光の入射角が、波長３５０〜
１１０５０ｎの光が全反射し得る臨界角１１〜２５以内
になり、かつ隣接する両凸状部（イ）の傾斜面３つによ
り入射光を入射面側に反射するような傾斜面であればよ
い。Note that the angle of inclination of the inclined surface 21) is not limited to the above-mentioned 45, and the angle of incidence of light on the inclined surface Qυ is within the range of wavelength 350 to
Any sloped surface that has a critical angle of 11 to 25 at which light of 11050n can be totally reflected, and that reflects the incident light toward the incident surface by the three sloped surfaces of the adjacent biconvex portions (A) is sufficient. .
また、各凸状部（イ）をシリコン酸化膜（９）の表面に
ストライプ状に形成しても、あるいはピラミツトスの感
度を大幅に向上することができるとともに、下層のデバ
イスの透過光による動作特性の低下を防止することがで
き、性能の優れた半導体立体回路素子としての積層構造
のイメージプロセッサを提供することが可能となり、そ
の効果は非常に大きい。Furthermore, even if the convex portions (a) are formed in stripes on the surface of the silicon oxide film (9), the sensitivity of the pyramid can be greatly improved, and the operating characteristics of the underlying device due to transmitted light can be improved. It is possible to prevent a decrease in the performance of the semiconductor three-dimensional circuit element, and it is possible to provide an image processor having a stacked structure as a semiconductor three-dimensional circuit element with excellent performance, which has a very large effect.
第１図ないし第４図はこの発明の半導体立体回路素子の
１実施例を示し、第１図は断面図、第２図（ａ）〜（ｄ
）は製造工程を示す断面図、第３図は製造途中の一部の
拡大断面図、第４図は一部の拡大断面図、第５図は従来
例の断面図である。1 to 4 show one embodiment of the semiconductor three-dimensional circuit element of the present invention, FIG. 1 is a sectional view, and FIGS. 2(a) to (d)
) is a sectional view showing the manufacturing process, FIG. 3 is an enlarged sectional view of a part in the middle of manufacturing, FIG. 4 is an enlarged sectional view of a part, and FIG. 5 is a sectional view of a conventional example.
Claims (1)
れ、少なくとも最上層に光センサデバイスを有する複数
のデバイスの積層構造の半導体立体回路素子において、
前記光センサデバイスと下層のデバイスとの間の層間絶
縁用の絶縁膜表面に、複数の傾斜面を有する複数の凸状
部を形成し、前記各傾斜面を、該傾斜面と隣接する前記
凸状部の傾斜面とにより入射光を入射光の入射面側に反
射する傾斜面としたことを特徴とする半導体立体回路素
子。(1) In a semiconductor three-dimensional circuit element having a stacked structure of a plurality of devices formed by sequentially stacking semiconductor thin films and insulating films and having a photosensor device in at least the uppermost layer,
A plurality of convex portions having a plurality of sloped surfaces are formed on a surface of an insulating film for interlayer insulation between the optical sensor device and a lower layer device, and each of the sloped portions is connected to the convex portion adjacent to the sloped surface. 1. A semiconductor three-dimensional circuit element, characterized in that the shaped portion has an inclined surface that reflects incident light toward the incident light incident surface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61152679A JPS639958A (en) | 1986-07-01 | 1986-07-01 | Semiconductor microwave circuit element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61152679A JPS639958A (en) | 1986-07-01 | 1986-07-01 | Semiconductor microwave circuit element |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS639958A true JPS639958A (en) | 1988-01-16 |
| JPH0316786B2 JPH0316786B2 (en) | 1991-03-06 |
Family
ID=15545742
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61152679A Granted JPS639958A (en) | 1986-07-01 | 1986-07-01 | Semiconductor microwave circuit element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS639958A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008153361A (en) * | 2006-12-15 | 2008-07-03 | Hitachi Ltd | Solid-state imaging device, and light detector and authentication equipment using the same |
-
1986
- 1986-07-01 JP JP61152679A patent/JPS639958A/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008153361A (en) * | 2006-12-15 | 2008-07-03 | Hitachi Ltd | Solid-state imaging device, and light detector and authentication equipment using the same |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0316786B2 (en) | 1991-03-06 |
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