JPS6394681A - Manufacture of insulated-gate field-effect semiconductor device - Google Patents
Manufacture of insulated-gate field-effect semiconductor deviceInfo
- Publication number
- JPS6394681A JPS6394681A JP24054586A JP24054586A JPS6394681A JP S6394681 A JPS6394681 A JP S6394681A JP 24054586 A JP24054586 A JP 24054586A JP 24054586 A JP24054586 A JP 24054586A JP S6394681 A JPS6394681 A JP S6394681A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor
- layers
- silicon
- layer
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 48
- 230000005669 field effect Effects 0.000 title claims abstract description 8
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 238000000034 method Methods 0.000 claims abstract description 29
- 239000013078 crystal Substances 0.000 claims abstract description 14
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 9
- 238000005229 chemical vapour deposition Methods 0.000 claims abstract description 9
- 239000012212 insulator Substances 0.000 claims description 17
- 230000000694 effects Effects 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 abstract description 13
- 239000010703 silicon Substances 0.000 abstract description 13
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 10
- 239000000969 carrier Substances 0.000 abstract description 10
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 abstract description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 5
- 239000012535 impurity Substances 0.000 abstract description 5
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 5
- 238000000137 annealing Methods 0.000 abstract description 4
- 238000005530 etching Methods 0.000 abstract description 4
- 238000005468 ion implantation Methods 0.000 abstract description 4
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 abstract description 3
- 239000001257 hydrogen Substances 0.000 abstract description 3
- 229910052739 hydrogen Inorganic materials 0.000 abstract description 3
- 239000011810 insulating material Substances 0.000 abstract 2
- 230000003993 interaction Effects 0.000 abstract 1
- 230000002093 peripheral effect Effects 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 34
- 239000010408 film Substances 0.000 description 17
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
- 239000007789 gas Substances 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 229910052757 nitrogen Inorganic materials 0.000 description 3
- 239000010409 thin film Substances 0.000 description 3
- 238000000576 coating method Methods 0.000 description 2
- 238000002425 crystallisation Methods 0.000 description 2
- 230000008025 crystallization Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 238000001771 vacuum deposition Methods 0.000 description 2
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- PZPGRFITIJYNEJ-UHFFFAOYSA-N disilane Chemical compound [SiH3][SiH3] PZPGRFITIJYNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000001962 electrophoresis Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- QSHDDOUJBYECFT-UHFFFAOYSA-N mercury Chemical compound [Hg] QSHDDOUJBYECFT-UHFFFAOYSA-N 0.000 description 1
- 229910052753 mercury Inorganic materials 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 230000000877 morphologic effect Effects 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 150000003376 silicon Chemical class 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- -1 silicon nitrides Chemical class 0.000 description 1
Abstract
Description
【発明の詳細な説明】
「発明の利用分野」
本発明は、高速動作を行うための絶縁ゲイト型電界効果
半導体装置の作製方法に関するもので、超ＬｓＩ 、超
々ＬＳＩに適用させる基礎ディバイスの製造方法を提案
するものである。DETAILED DESCRIPTION OF THE INVENTION Field of Application of the Invention The present invention relates to a method for manufacturing an insulated gate field effect semiconductor device for high-speed operation, and a method for manufacturing a basic device applied to ultra-LSI and ultra-super LSI. This is what we propose.
「従来の技術」
絶縁ゲイト型電界効果半導体装置（以下ＩＧ、ＦＥＴと
いう）は、一対の不純物領域であるソース領域、ドレイ
ン領域とその間に設けられたチャネル形成領域とよりな
り、このチャネル形成領域の状態をゲイト電極に印加さ
れた電界により制御するものである。そしてこのチャネ
ル形成領域は華なる１種類の単結晶半導体材料例えばシ
リコン半導体よりなり、このシリコン半導体にＰ又はＮ
型の不純物をドープしてスレッシュホールド電圧の制御
、ソース、ドレイン間のバンチスルーの防止を行ってき
た。"Prior Art" An insulated gate field effect semiconductor device (hereinafter referred to as IG, FET) consists of a pair of impurity regions, a source region and a drain region, and a channel forming region provided between them. The state is controlled by an electric field applied to the gate electrode. This channel forming region is made of one kind of single crystal semiconductor material such as silicon semiconductor, and this silicon semiconductor is made of P or N.
Type impurities have been doped to control the threshold voltage and prevent bunch-through between the source and drain.
「発明の解決しようとする問題」
しかし、この技術ではこれまでキャリアが半導体とゲイ
ト絶縁膜との界面およびそのごく近接した半導体領域に
集中して流れ、界面散乱に伴いキャリアの移動度も電子
で約３００ｃｍ”Ｖ／ｓｅｃ 、ホールで１５０ｃｍ”
ν／ｓｅｃ Ｌかない。``Problem to be solved by the invention'' However, in this technology, carriers have been concentrated at the interface between the semiconductor and the gate insulating film and the semiconductor region in close proximity to the interface, and due to interface scattering, carrier mobility has also been reduced by electrons. Approximately 300cm"V/sec, 150cm in the hole"
ν/sec L is not enough.
これは界面散乱を用いつつ、少数キャリアをチャネル形
成領域に注入したためである。さらにソース、ドレイン
間の短チヤネル化に伴い、このチャネル形成領域をＮチ
ャネルＩＧ、ＦＥＴの場合Ｐ型とする。しかもこの程度
は短チヤネル化に伴い、益々高濃度化しなければならな
い。このため、さらにキャリアの移動度が小さくなって
しまうという二重の欠点があった。This is because minority carriers were injected into the channel forming region while using interface scattering. Furthermore, with the shortening of the channel between the source and drain, this channel forming region is made P type in the case of N channel IG and FET. Moreover, as the channels become shorter, the concentration must become higher and higher. For this reason, there was a double drawback in that the mobility of carriers further decreased.
このため、チャネル長を短くしてもソース・ドレイン間
に空乏層がひろがりにくいこと、さらにキャリアを表面
伝導（界面散乱を伴う伝導）からバルク伝導（界面の散
乱を伴わない伝導）にすることが求められていた。本発
明はこれらを改良せんとするものである。For this reason, even if the channel length is shortened, the depletion layer is difficult to spread between the source and drain, and furthermore, it is difficult to change carriers from surface conduction (conduction with interface scattering) to bulk conduction (conduction without interface scattering). It was wanted. The present invention aims to improve these.
「問題を解決するための手段」
本発明はこれらの問題を解決するため、ＩＧ、ＦＥＴの
チャネル形成領域に半導体層−絶縁体（半絶縁体を含む
）層−半導体層・・・の繰り返しの多層構造からなるス
ーパーラティス（超格子）構造をキャリアの移動方向に
沿って面を有すべく積層する方法として光ＣＶＤ法また
は光エピタキシアル法を用いたものである。"Means for Solving the Problems" In order to solve these problems, the present invention has a structure in which a semiconductor layer, an insulator (including semi-insulator) layer, a semiconductor layer, etc. are repeatedly formed in the channel formation region of IG and FET. A photo-CVD method or a photo-epitaxial method is used as a method for laminating a super lattice structure consisting of a multilayer structure so as to have a surface along the carrier movement direction.
この場合、半導体層および絶縁体または半絶縁体層を光
ＣＶＤ法およびその後の光ビームアニールまたは光エピ
タキシアル成長法を用いて形成し、それぞれの層の厚さ
は５〜１００人、好ましくは１０〜３０人とし、それぞ
れの層におけるエネルギバンド巾はそれを挟む層のエネ
ルギバンドの影舌を受けて変形せしめるいわゆる超格子
構造を有せしめた。その結果、エネルギバンド端が変成
されているため、眉間の界面と平行に移動するキャリア
にとって界面を実質的に除去できる。例えば、シリコン
半導体２０八−窒化珪素（Ｓｉ３Ｎ４−ｘ Ｏ＜Ｘ＜４
） ２０人−シリコン半導体２０人・・・と少な（もシ
リコン半導体を２層以上設けたものである。これを光Ｃ
ＶＤ法を用いて形成し、さらにその後光ビームアニール
工程を加えて単結晶化した。他の方法としては光エピタ
キシアル成長せしめた。In this case, the semiconductor layer and the insulator or semi-insulator layer are formed using a photo-CVD method followed by a light beam annealing or a photoepitaxial growth method, and each layer has a thickness of 5 to 100 layers, preferably 10 to 10 layers. ~30 people, and a so-called superlattice structure was created in which the energy band width in each layer was deformed by the influence of the energy bands of the layers sandwiching it. As a result, the energy band edges have been transformed so that the interface can be virtually eliminated for carriers moving parallel to the glabellar interface. For example, silicon semiconductor 208-silicon nitride (Si3N4-x O<X<4
) 20 people - silicon semiconductor 20 people... (also has two or more layers of silicon semiconductor. This is an optical C
It was formed using the VD method, and then a light beam annealing process was added to form a single crystal. Another method was photoepitaxial growth.
そのため、各半導体のそれぞれに十分均等にキャリア注
入させるべく、各層の端面ば各層の界面に垂直またはゲ
イト絶縁膜より離れる（内部に至る）に従ってチャネル
形成領域を中挟（よりチャネル長を短くする方向）にす
ることが好ましい。Therefore, in order to inject carriers sufficiently evenly into each semiconductor, the channel formation region is sandwiched between the end faces of each layer perpendicular to the interface between the layers or away from the gate insulating film (into the interior) (in the direction to shorten the channel length). ) is preferable.
「作用」
かかる場合、光ＣＶＤ法または光エピタキシアル成長法
を用いてこの５〜１００人好ましくは１０〜３０人の膜
厚の被膜を形成を行った。これは他の真空蒸着法、スパ
ッタ法、減圧ＣＶＤ法、ＥＣＲプラズマＣＶＤ法に比べ
ても、きわめて優れたものである。"Operation" In this case, a film with a thickness of 5 to 100 people, preferably 10 to 30 people, was formed using a photoCVD method or a photoepitaxial growth method. This is extremely superior compared to other vacuum evaporation methods, sputtering methods, low pressure CVD methods, and ECR plasma CVD methods.
それは光ＣＶＤ法は被膜形成の過程がクラスタ表面泳動
理論に基づいてなされているためである。即ち、他の被
膜形成は単に被形成面に積層してゆくのみで、ピンホー
ルがあるとそのホールも大きく拡大する方向に形成され
る。また形成される被膜がグレイン化しやすい。他方、
光ＣＶＤ法はクラスタ状態（会合分子状態）の反応性気
体が被形成面を泳動する。そして外皮を被形成面に蒸着
する。This is because the process of film formation in the photoCVD method is based on the theory of cluster surface migration. In other words, other coatings are simply layered on the surface to be formed, and if a pinhole is present, the hole is also formed in a direction that greatly expands. Furthermore, the formed film tends to become grainy. On the other hand,
In the photoCVD method, a reactive gas in a cluster state (associative molecule state) migrates on a surface on which formation is to be performed. Then, the outer skin is deposited on the surface to be formed.
加えてこの泳動により被形成面に保存されているエネル
ギのより少ない方向に移動する。結果として被形成面を
より同じ厚さにするように形成し、ピンホールも積極的
に充填する方向に形成させる。In addition, this electrophoresis causes the particles to move in a direction where less energy is stored on the surface on which they are formed. As a result, the surfaces to be formed are formed to have a more uniform thickness, and pinholes are also formed in a direction in which they are actively filled.
加えて、半導体層を２つの広いエネルギバンド巾を有す
る層で挟むため、この半導体が高温処理で変成すること
がない。例えばシリコン半導体（厚さ２０人）を窒化珪
素（ＳｉＪ４−ｘ Ｏ＜Ｘ＜４）で挟むとこの窒化珪素
により押さえられ、面方向の結晶化のみが生じやすく、
横方向のキャリアの移動に優れた結晶異方性を有し得る
。これに光ＣＶＤ法で形成したものをその後工程で光ビ
ームアニールを行うことにより特性の改善を可能とする
。In addition, since the semiconductor layer is sandwiched between two layers having a wide energy band width, the semiconductor is not metamorphosed by high-temperature treatment. For example, when a silicon semiconductor (20 mm thick) is sandwiched between silicon nitride (SiJ4-x O<X<4), it is held down by the silicon nitride, and crystallization tends to occur only in the plane direction.
It can have crystal anisotropy with excellent lateral carrier movement. The characteristics can be improved by performing light beam annealing on the material formed by photo-CVD in a subsequent step.
以下に実施例に従い本発明を説明する。The present invention will be described below with reference to Examples.
「実施例１」
第１図は本発明のＩＧ、ＦＥＴの製造工程を示す縦断面
図である。"Example 1" FIG. 1 is a longitudinal cross-sectional view showing the manufacturing process of the IG and FET of the present invention.
第１図（Ａ）において、単結晶半導体として例えばシリ
コン半導体を用いた。この半導体の表面を十分清浄にし
た後、光ＣＶＯ法を用いシリコン半導体層を２５人の厚
さに形成する。さらに、窒化珪素（ＳｉＪ＊−ｘ Ｑ＜
χ〈４）をそれに続き形成する。さらに再びシリコン半
導体を形成する。これを２〜５０回繰り返し、超格子構
造を作る。この方法はこれまで末完門人により開発され
てきた光ＣＶＯ装置（ｈシー１）を用いた。即ち、反応
炉内に基板を保持し、低圧水銀灯（１８５ｎｍ）を用い
て、この紫外光で基板の表面を照射しつつ反応炉内の圧
力を１０ｔｏｒｒに保持した。基板の温度は２００〜５
００℃、例えば４００℃とした。反応性気体としてジシ
ラン（Ｓｉｚｌ１６）を用いた。そして所定の時間を経
て厚さ１０〜１００人、例えば２５人のシリコン半導体
を形成した。その後マイクロコンピュータにより制御さ
せつつ、この系にＮｕ３／Ｓｉ ｚＨｂ ＝ ０．１〜
１例えば０．３として同様に光ＣＶＯ法により５ｉ３Ｎ
ｎ−ｘ （０＜Ｘ＜４）を形成した。In FIG. 1A, for example, a silicon semiconductor is used as the single crystal semiconductor. After the surface of this semiconductor is sufficiently cleaned, a silicon semiconductor layer is formed to a thickness of 25 nm using a photo-CVO method. Furthermore, silicon nitride (SiJ*-x Q<
χ<4) is subsequently formed. Furthermore, a silicon semiconductor is formed again. This is repeated 2 to 50 times to create a superlattice structure. This method used an optical CVO device (hC1) developed by Suekan. That is, the substrate was held in a reactor, and the pressure in the reactor was maintained at 10 torr while the surface of the substrate was irradiated with ultraviolet light using a low-pressure mercury lamp (185 nm). The temperature of the board is 200-5
00°C, for example 400°C. Disilane (Sizl16) was used as the reactive gas. After a predetermined period of time, a silicon semiconductor having a thickness of 10 to 100 layers, for example 25 layers, was formed. Thereafter, under the control of a microcomputer, this system was given Nu3/SizHb = 0.1~
1, for example, 5i3N using the photoCVO method as 0.3.
n-x (0<X<4) was formed.
この窒化珪素膜は低級窒化珪素膜である。この窒化珪素
膜を同様に１０〜１００人例えば２５人の厚さに形成し
た。こうして半導体層および絶縁体層（または半絶縁体
層）の形成をｎ回繰り返し行い、少なくとも２層の半導
体層−最には２〜５０層をマイクロコンピュータにより
制御して形成した。This silicon nitride film is a low grade silicon nitride film. This silicon nitride film was similarly formed to a thickness of 10 to 100, for example 25. In this way, the formation of the semiconductor layer and the insulator layer (or semi-insulator layer) was repeated n times, and at least two semiconductor layers, in total 2 to 50 layers, were formed under the control of a microcomputer.
次にこれら全体を水素雰囲気に浸しつつ、レーザ光、例
えば窒素レーザにより光アニールを行った。すると基板
（１０）が単結晶のため、半導体層（ｌ−１） 、 （
１−３） ・・・は単結晶化される。また窒化珪素で
ある（１−２） 、 （１−４） ・・・は窒素の添
加量に従い単結晶、歪単結晶または非単結晶の構造をと
り得る。Next, the entire structure was immersed in a hydrogen atmosphere and optically annealed using a laser beam, for example, a nitrogen laser. Then, since the substrate (10) is a single crystal, the semiconductor layers (l-1), (
1-3) ... is made into a single crystal. Furthermore, silicon nitrides (1-2), (1-4), etc. can have a single crystal, strained single crystal, or non-single crystal structure depending on the amount of nitrogen added.
第１図（Ａ）はその−例として半導体層（１−１） 、
（１〜３）、絶縁体または半絶縁体層（１−２） 、
（１−４）を形成し、この積層体を（１）としている
。FIG. 1(A) shows, as an example, a semiconductor layer (1-1),
(1-3), insulator or semi-insulator layer (1-2),
(1-4) was formed, and this laminate was designated as (1).
この後、本発明においてはマスク（２）を形成して、そ
のパターンの外側を異方性エソチンングをし、少なくと
も多層部（１）の領域を除去した。さらにこの除去した
部分に絶縁物（４）を充填した。Thereafter, in the present invention, a mask (2) was formed, and anisotropic etching was performed on the outside of the pattern to remove at least the region of the multilayer part (1). Furthermore, this removed portion was filled with an insulator (4).
この絶縁物はいわゆるトレンチ構造の形成方法と同様の
プロセスに従った。その後マスク（２）を除去し、第１
図（Ｂ）を得た。This insulator followed a process similar to the method of forming a so-called trench structure. Then remove the mask (2) and
Figure (B) was obtained.
その後、第１図（Ｃ）に示される如（、ゲイト絶縁膜（
５）およびゲイト電極（８）を形成した。ゲイト絶縁膜
は光ＣＶＤ法の酸化珪素膜（厚さ２００人）とした。ゲ
イト電極は多結晶シリコン、ＷＳｉｚ、 ＴｔＳｉ２ま
たは半導体−金属多層構造であってもよい。Thereafter, as shown in FIG. 1(C), the gate insulating film (
5) and a gate electrode (8) were formed. The gate insulating film was a silicon oxide film (thickness: 200 mm) produced by photo-CVD method. The gate electrode may be polycrystalline silicon, WSiz, TtSi2 or a semiconductor-metal multilayer structure.
この後、ソース（６）、ドレイン（７）をイオン注入法
によりその不純物濃度が１ｏ１７〜１Ｑ１９ｃ「３とな
るようにした。この時、このソース・ドレインの端面ば
積層体（１）に対し垂直となるべく努めた。Thereafter, the source (6) and drain (7) were implanted by ion implantation so that their impurity concentration was 1017~1Q19c'3.At this time, the end faces of the source and drain were perpendicular to the stacked body (1). I tried my best to do so.
この後これら全体に光ｃｖＤ法を用いＳｉＨ４と０２の
反応により０．５μの厚さに酸化珪素膜を作製した。Thereafter, a silicon oxide film with a thickness of 0.5 .mu.m was formed over the entire structure by a reaction between SiH4 and 02 using a photo-CVD method.
さらにそれらに対し、ＥＣＲ（電子サイクロトロン共鳴
）を用いた異方性エソチンングを施し、ゲイト電極の側
周辺のみを（９）に示す如く残し他部をエツチング除去
をした。Furthermore, they were subjected to anisotropic etching using ECR (electron cyclotron resonance), leaving only the area around the gate electrode as shown in (9), and etching away the other areas.
更に１ ×１Ｑ１９〜２ ＸＩＯ”ｃｎ＋−３の高濃度
のイオン注入によりコンタクトのオーム接触用およびソ
ース、ドレインの低シート抵抗化を行う領域（６’）。Further, there is a region (6') in which ion implantation at a high concentration of 1×1Q19-2XIO"cn+-3 is performed for ohmic contact and to lower the sheet resistance of the source and drain.
（７゛）を形成した。(7゛) was formed.
さらにこれらの熱アニールを行い、その後層間絶縁物（
１３）を酸化珪素により形成した。さらに電極用穴あけ
を行い、ソースの電極・リード（１１）、ドレインの電
極・リード（１２）を公知のアルミニュームにより形成
させた。These are further thermally annealed, and then the interlayer insulator (
13) was formed from silicon oxide. Furthermore, holes for electrodes were formed, and a source electrode/lead (11) and a drain electrode/lead (12) were formed from known aluminum.
かくして形成されたＩＧ、ＦＥＴはチャネル長１μを形
成する時、チャネル形成領域（２０）の半導体がアンド
ープまたは第１図（Ｃ）にてゲイト絶縁物を形成した後
のスレッシュホールド電圧制御用に必要な不純物の添加
の程度であるにもかかわらず、ソース、ドレイン間の電
圧が例えば５νでパンチスルーを観察しなかった。また
Ｃ、Ｔ、５ａｈＯ式により求めた移動度は７５０ｃｍ”
Ｖ／ｓｅｃを有しており、これまではＩＧ、ＦＥＴが３
００ｃｍ”Ｖ／ｓｅｃ程度であるに比べて約２．５倍の
移動度を得ることができた。When forming a channel length of 1μ, the IG and FET thus formed are necessary for threshold voltage control after the semiconductor in the channel forming region (20) is undoped or a gate insulator is formed in FIG. 1(C). Despite the degree of impurity addition, punch-through was not observed when the voltage between the source and drain was, for example, 5ν. In addition, the mobility determined by the C, T, 5ahO formula is 750 cm"
V/sec, and up until now IG and FET were 3
It was possible to obtain a mobility approximately 2.5 times higher than that of approximately 0.00 cm"V/sec.
このキャリア移動度は超格子の結晶性の向上に伴い、さ
らに向上させることができるものと推定される。It is estimated that this carrier mobility can be further improved as the crystallinity of the superlattice improves.
さらに第３図は第１図（Ｄ）におけるＡ−Ａ’のエネル
ギバンド図であり、実線がモホロジ的なエネルギバンド
図を示す。図の破線図より明らかな如（、キャリア（こ
こでは電子）にとって最も安定な領域が多数（１−３）
、 （１−５） ・・・存在し、かつ界面より離れ
た位置にエネルギバンド的に最も安定な領 １域がある
ことがわかる。このため第３図（Ｂ）に示す如くに電圧
を印加されても、キャリアがゲイト絶縁膜との界面のみ
に集中することを防ぐことができる。Furthermore, FIG. 3 is an energy band diagram of AA' in FIG. 1(D), and the solid line indicates a morphological energy band diagram. As is clear from the broken line diagram in the figure, there are many regions (1-3) that are most stable for carriers (electrons here).
, (1-5)... and it can be seen that there is a region 1 that is most stable in terms of energy band at a position away from the interface. Therefore, even if a voltage is applied as shown in FIG. 3(B), carriers can be prevented from being concentrated only at the interface with the gate insulating film.
「実施例２」 第２図は本発明の他の実施例を示す。"Example 2" FIG. 2 shows another embodiment of the invention.
図面において第２図（Ａ） 、 （Ｂ）に実施例１と同
様に形成した。In the drawings, the structure shown in FIGS. 2(A) and 2(B) was formed in the same manner as in Example 1.
更に第２図（Ｃ）において、ソース（６）、ドレイン（
７）を表面側（ゲイト絶縁物に接する側）を低濃度とし
、他部（ゲイト絶縁膜より離れた内部側）に高濃度領域
を作った。即ち、ソース（６）、ドレイン（７）の最高
濃度領域を界面ではなく内部にすべくイオン注入を行っ
た。するとソース、ドレイン間の距離（チャネル長）は
ゲイト絶縁膜との界面に近ずくに従って長くなり、内部
により短い層を存在させることができる。その結果、キ
ャリアはゲイト絶縁膜の界面より離れた内部の半導体層
をより通過やすくなり、より表面散乱の形容をさけるこ
とができ得る。Furthermore, in FIG. 2(C), the source (6), the drain (
7), the surface side (the side in contact with the gate insulator) was made to have a low concentration, and the other part (the inside side away from the gate insulating film) was made to have a high concentration region. That is, ion implantation was performed so that the highest concentration regions of the source (6) and drain (7) were located inside the device rather than at the interface. Then, the distance between the source and drain (channel length) becomes longer as it approaches the interface with the gate insulating film, allowing a shorter layer to exist inside. As a result, carriers can more easily pass through the internal semiconductor layer away from the interface of the gate insulating film, and surface scattering can be further avoided.
更に実施例１と同様の工程を経て、第２図（Ｂ）の縦断
面図を得た。Further, the same steps as in Example 1 were carried out to obtain the longitudinal cross-sectional view shown in FIG. 2(B).
この図面において、キャリア移動度８５０ｃｍｚＶ／ｓ
ｅｃを得た。この結果はこれまでのいわゆるショートチ
ャネルＩＧ、ＦＥＴではみられない大きな値である。In this drawing, the carrier mobility is 850 cmzV/s
I got ec. This result is a large value that has not been seen in conventional so-called short channel IGs and FETs.
「実施例３」
この実施例は第１図または第２図において第２図（＾）
の超格子の作製方法に関し光エピタキシアル成長方法を
用いたものである。"Example 3" This example is shown in Figure 2 (^) in Figure 1 or Figure 2.
This method uses a photoepitaxial growth method to fabricate a superlattice.
即ち、実施例１と同様の装置を用いた。基板温度は５０
０℃、圧力１０ｔｏｒｒとし、反応性気体はＳ ｉ ｚ
Ｈｂに加えてＨ２Ｓ１Ｆ２を同じ程度注入した。加え
て水素を５ｉｚＮ、の２０倍の量導入した。その他は実
施例１と同様である。すると半導体層をエピタキシアル
成長をさせることが可能となった。That is, the same apparatus as in Example 1 was used. The substrate temperature is 50
The temperature was 0°C, the pressure was 10 torr, and the reactive gas was S i z
In addition to Hb, H2S1F2 was injected to the same extent. In addition, hydrogen was introduced in an amount 20 times that of 5 izN. The rest is the same as in Example 1. This made it possible to grow the semiconductor layer epitaxially.
「効果」
本発明によりこれまで単に可能性のみが論じられてきた
超格子の作製を光ＣＶＤ法または光エピタキシアル成長
法を用いて具体的に単結晶シリコンＩＧ、ＦＥＴに適用
した。その結果十分大なる工業的効果即ちショートチャ
ネル化を伴うドレイン電圧低下の防止、キャリア移動度
の向上に伴う高速化を達成した。"Effects" According to the present invention, the fabrication of a superlattice, which has so far only been discussed as a possibility, was specifically applied to single-crystal silicon IGs and FETs using a photo-CVD method or a photo-epitaxial growth method. As a result, we have achieved sufficiently large industrial effects, namely, prevention of drain voltage drop due to short channel formation, and speeding up due to improved carrier mobility.
特に光ＣＶＤ法または光エピタキシアル成長法は極薄膜
を均一な厚さに形成するのに優れており、また、気体の
入れ換えのみにより広いエネルギバンド巾の層と狭いエ
ネルギバンド巾の層とを作ることができる。そしてその
厚さも５〜１００人、好ましくは１０〜３０人の厚さで
再現性よく形成することができ、他の真空蒸着法、スパ
ッタ法に比べきわめて優れたものであった。特に被膜作
製時、その下側の極薄膜に何らの損傷を与えない点はき
わめて注目に値する。In particular, the photo-CVD method or the photo-epitaxial growth method is excellent for forming ultra-thin films with uniform thickness, and can also create layers with a wide energy band width and layers with a narrow energy band width simply by replacing gas. be able to. The thickness could be formed by 5 to 100 people, preferably 10 to 30 people, with good reproducibility, which was extremely superior to other vacuum evaporation methods and sputtering methods. It is especially noteworthy that the coating does not cause any damage to the ultra-thin film underneath.
本発明は、単結晶のシリコン半導体の層と窒化珪素の層
との多層構造とした。しかし窒化珪素の替わりに酸化珪
素（ＳｉＯｚ−ｘ Ｏ＜Ｘ＜２）または炭化珪素（Ｓｉ
ｘＣ＋−ｘ Ｏ＜Ｘ４）を用いてもよい。The present invention has a multilayer structure including a single crystal silicon semiconductor layer and a silicon nitride layer. However, silicon oxide (SiOz-x O<X<2) or silicon carbide (Si
xC+−xO<X4) may also be used.
さらに本発明は積層的に５ＯＩ（絶縁膜上の半導体単結
晶化）プロセスを用いている。その結果、三次元素子構
成に適用することができる。また薄膜トランジスタに対
しても適用することができる。Further, the present invention uses a 5OI (single crystallization of semiconductor on an insulating film) process in a layered manner. As a result, it can be applied to tertiary element configurations. It can also be applied to thin film transistors.
第１図および第２図は本発明の製造工程を示す縦断面図
である。
第３図は本発明の超格子構造を示す一例である。FIGS. 1 and 2 are longitudinal sectional views showing the manufacturing process of the present invention. FIG. 3 is an example showing the superlattice structure of the present invention.
Claims (1)
域の形成を、単結晶半導体上に半導体層と絶縁体または
半絶縁体層との多層構造を構成せしめ、それらの各層が
互いに量子論的に相互作用を生ぜしめる程度の厚さに形
成させるに際し、かかる多層構造を光ＣＶＤ法または光
エピタキシァル成長法を用いて形成せしめることを特徴
とする絶縁ゲイト型電界効果半導体装置の作製方法。 ２、絶縁ゲイト型電界効果半導体装置のチャネル形成領
域の形成を、単結晶半導体上に半導体層と絶縁体または
半絶縁体層との多層構造を構成せしめ、それらの各層が
互いに量子論的に相互作用を生ぜしめる程度の厚さに形
成させるに際し、かかる多層構造を光ＣＶＤ法または光
エピタキシァル成長法により形成せしめる工程と、ゲイ
ト絶縁膜およびゲイト電極を形成する工程と、前記ゲイ
ト電極下のチャネル形成領域を挟んでソースおよびドレ
インを形成する工程とを有することを特徴とする絶縁ゲ
イト型電界効果半導体装置の作製方法。[Claims] 1. The channel formation region of an insulated gate field effect semiconductor device is formed by configuring a multilayer structure of a semiconductor layer and an insulator or semi-insulator layer on a single crystal semiconductor, and each of these layers Fabrication of an insulated gate field effect semiconductor device characterized in that such a multilayer structure is formed using a photo-CVD method or a photo-epitaxial growth method when the multilayer structure is formed to a thickness such that they mutually interact quantum theory. Method. 2. The channel formation region of an insulated gate field effect semiconductor device is formed by configuring a multilayer structure of a semiconductor layer and an insulator or semi-insulator layer on a single crystal semiconductor, and each of these layers mutually quantum-theoretically interacts with each other. When forming the multilayer structure to a thickness sufficient to produce the effect, there are a step of forming such a multilayer structure by a photo-CVD method or a photo-epitaxial growth method, a step of forming a gate insulating film and a gate electrode, and a step of forming a channel under the gate electrode. 1. A method for manufacturing an insulated gate field effect semiconductor device, comprising the step of forming a source and a drain with a region in between.
Priority Applications (6)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24054586A JPS6394681A (en) | 1986-10-08 | 1986-10-08 | Manufacture of insulated-gate field-effect semiconductor device |
| US07/102,841 US4908678A (en) | 1986-10-08 | 1987-09-30 | FET with a super lattice channel |
| US07/342,854 US5021839A (en) | 1986-10-08 | 1989-04-25 | FET with a super lattice channel |
| US07/406,859 US5008211A (en) | 1986-10-08 | 1989-09-14 | Method for forming FET with a super lattice channel |
| US07/466,955 US5055887A (en) | 1986-10-08 | 1990-01-18 | Fet with a super lattice channel |
| US07/512,026 US4988634A (en) | 1986-10-08 | 1990-04-16 | Method for forming FET with a super lattice channel |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24054586A JPS6394681A (en) | 1986-10-08 | 1986-10-08 | Manufacture of insulated-gate field-effect semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6394681A true JPS6394681A (en) | 1988-04-25 |
Family
ID=17061121
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP24054586A Pending JPS6394681A (en) | 1986-10-08 | 1986-10-08 | Manufacture of insulated-gate field-effect semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6394681A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6069049A (en) * | 1995-06-06 | 2000-05-30 | International Business Machines Corporation | Shrink-wrap collar from DRAM deep trenches |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5984775A (en) * | 1982-10-29 | 1984-05-16 | 株式会社東芝 | Collector for apparatus |
| JPS6127681A (en) * | 1984-07-17 | 1986-02-07 | Res Dev Corp Of Japan | Field effect transistor having channel part of superlattice construction |
-
1986
- 1986-10-08 JP JP24054586A patent/JPS6394681A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5984775A (en) * | 1982-10-29 | 1984-05-16 | 株式会社東芝 | Collector for apparatus |
| JPS6127681A (en) * | 1984-07-17 | 1986-02-07 | Res Dev Corp Of Japan | Field effect transistor having channel part of superlattice construction |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6069049A (en) * | 1995-06-06 | 2000-05-30 | International Business Machines Corporation | Shrink-wrap collar from DRAM deep trenches |
| US6399976B1 (en) | 1995-06-06 | 2002-06-04 | International Business Machines Corporation | Shrink-wrap collar for DRAM deep trenches |
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