JPS6394668A - Storage device - Google Patents
Storage deviceInfo
- Publication number
- JPS6394668A JPS6394668A JP61240574A JP24057486A JPS6394668A JP S6394668 A JPS6394668 A JP S6394668A JP 61240574 A JP61240574 A JP 61240574A JP 24057486 A JP24057486 A JP 24057486A JP S6394668 A JPS6394668 A JP S6394668A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- polycrystalline
- gate
- protrusions
- oxide film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 claims abstract description 28
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 239000012535 impurity Substances 0.000 claims description 3
- 239000004065 semiconductor Substances 0.000 claims description 3
- 239000012212 insulator Substances 0.000 claims 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 7
- 238000000034 method Methods 0.000 abstract description 6
- 230000003647 oxidation Effects 0.000 abstract description 3
- 238000007254 oxidation reaction Methods 0.000 abstract description 3
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 2
- 238000005468 ion implantation Methods 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 16
- 230000007423 decrease Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/038—Making the capacitor or connections thereto the capacitor being in a trench in the substrate
- H10B12/0383—Making the capacitor or connections thereto the capacitor being in a trench in the substrate wherein the transistor is vertical
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体メモリ装置に関し、特にトレンチ型キ
ャパシタを有するＤＲＡＭの構造に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device, and more particularly to a DRAM structure having a trench type capacitor.
本発明は、トレンチ型キャパシタを有するＤＲＡＭに於
いて、半忠体基板に形成された複数の柱状突起部の下部
にその誘電体層を介してキャパシタ電極を設け、その上
部にはゲート絶縁膜を介して前記キャパシタ電極と絶縁
してスイッチングトランジスタのゲート電極を設け、前
記複数の柱状突起部を結ぶゲート電極を複数形成し、前
記柱状突起部の先端を中心にして前記スイッチングトラ
ンジスタを複数に分割する不純物領域を前記柱状突起部
に形成し、その柱状突起部の先端部を所定方向に接続す
る複数の配線層を前記ゲート電極と絶縁した状態で設け
るようにメモリ装置を構成することによって、従来と同
等の集積度を保ちつつリーク電流を低下させたものであ
る。In a DRAM having a trench type capacitor, the present invention provides a capacitor electrode at the bottom of a plurality of columnar projections formed on a semi-fidelity substrate through a dielectric layer, and a gate insulating film on the top of the capacitor electrode. A gate electrode of a switching transistor is provided insulated from the capacitor electrode through a gate electrode, a plurality of gate electrodes are formed to connect the plurality of columnar protrusions, and the switching transistor is divided into a plurality of parts around the tips of the columnar protrusions. By configuring the memory device in such a way that an impurity region is formed in the columnar protrusion and a plurality of wiring layers connecting the tips of the columnar protrusion in a predetermined direction are provided in a state insulated from the gate electrode, the memory device is improved. This reduces leakage current while maintaining the same degree of integration.
ＤＲＡＭの高密度化が進むにつれて、基板内にトレンチ
を掘り、その中にキャパシタを形成するトレンチ型キャ
パシタを利用したＤＲＡＭがその主流に成りつつある。As the density of DRAMs increases, DRAMs using trench-type capacitors, in which a trench is dug in a substrate and a capacitor is formed in the trench, are becoming mainstream.
そのトレンチ型キャパシタを有するＤＲＡＭの従来例（
特願昭６１−１３４３８３号）を第３図に基づいて説明
する。Ｐ−型基板１内に掘られたトレンチ表面には、キ
ャパシタ酸化膜６が形成され、第１多結晶Ｓｔ層５によ
って埋められる。この第１多結晶Ｓｉ層５はキャパシタ
プレートとなる。そのキャパシタプレートを形成した後
、その表面を酸化膜でキャップし、その上に第２多結晶
５ｉｌｉｌＯを成長させる。この第２多結晶５ｉＦＩＯ
がゲート電極となり、キャパシタより上部のトレンチの
側壁部分がゲート酸化膜となる。ゲート電極となる第２
多結晶Ｓｉ層を酸化膜により被った後、ドナーをイオン
注入してＳ／ＤｊＪ域９を形成しＰＪ線１２によりビッ
トラインを配線する。Conventional example of DRAM with trench type capacitor (
(Japanese Patent Application No. 134383/1983) will be explained based on FIG. A capacitor oxide film 6 is formed on the surface of the trench dug in the P- type substrate 1, and is filled with a first polycrystalline St layer 5. This first polycrystalline Si layer 5 becomes a capacitor plate. After forming the capacitor plate, its surface is capped with an oxide film, and a second polycrystalline 5ililO is grown thereon. This second polycrystalline 5iFIO
becomes the gate electrode, and the side wall portion of the trench above the capacitor becomes the gate oxide film. The second electrode becomes the gate electrode.
After covering the polycrystalline Si layer with an oxide film, donor ions are implanted to form S/DjJ regions 9 and bit lines are wired by PJ lines 12.
第３図に示されるように、従来のトレンチ型キャパシタ
を用いたＤＲＡＭのセルに於いては、キャパシタプレー
トとなる第１多結晶５ｉＪ５５の上に、トランスファゲ
ートとなる第２多結晶Ｓｉ層１ｏが形成されている。こ
の従来の構造では、トランスファゲートが一段しかない
ため、キャパシタからリークする電荷の量を無視するこ
とができず、メモリセルの電荷保持特性を改善する事に
限界があった。As shown in FIG. 3, in a DRAM cell using a conventional trench-type capacitor, a second polycrystalline Si layer 1o, which becomes a transfer gate, is placed on a first polycrystalline 5iJ55, which becomes a capacitor plate. It is formed. In this conventional structure, since there is only one stage of transfer gate, the amount of charge leaking from the capacitor cannot be ignored, and there is a limit to improving the charge retention characteristics of the memory cell.
トレンチ内の第２多結晶５ｉｌｉの深さを大きくして、
キャパシタプレート５とＳ／ＤｊＪ域９との距離つまり
ゲート長を長くすれば、電荷のリークを低下させること
はできるが、一方で、トランジスタのＧ、が低下しメモ
リのドライブ能力が落ち、また付加容量が増加してアク
セスタイムが遅くなると言う問題が生じる。従ってトラ
ンジスタのゲート長しはむやみに長くすることが出来ず
、これによってリーク電流を低下させることは困難であ
った。By increasing the depth of the second polycrystalline 5ili in the trench,
By increasing the distance between the capacitor plate 5 and the S/DjJ region 9, that is, the gate length, it is possible to reduce charge leakage, but on the other hand, the G of the transistor decreases, the memory drive ability decreases, and the additional A problem arises in that the increased capacity slows down access time. Therefore, the gate length of the transistor cannot be increased unnecessarily, and it has been difficult to reduce leakage current.
本発明は、半導体基板に形成された複数の柱状突起部の
下部にその誘電体層を介してキャパシタ電極を設け、そ
の上部にはゲート絶縁膜を介して前記キャパシタ電極と
絶縁してスイッチングトランジスタのゲート電極を設け
、前記複数の柱状突起部を結ぶゲート電極を複数形成し
、前記柱状突起部の先端を中心にして前記スイッチング
トランジスタを複数に分割する不純物領域を前記柱状突
起部に形成し、その柱状突起部の先端部を所定方向に接
続する複数の配線層を前記ゲート電極と絶縁した状態で
設けるようにメモリ装置を構成することによって、前記
問題点を解決した。The present invention provides a capacitor electrode at the bottom of a plurality of columnar protrusions formed on a semiconductor substrate through a dielectric layer thereof, and insulates the capacitor electrode from the capacitor electrode through a gate insulating film at the top of the capacitor electrode to form a switching transistor. providing a gate electrode, forming a plurality of gate electrodes connecting the plurality of columnar protrusions, forming an impurity region in the columnar protrusion that divides the switching transistor into a plurality of parts around the tip of the columnar protrusion; The above problem has been solved by configuring the memory device so that a plurality of wiring layers connecting the tips of the columnar protrusions in a predetermined direction are provided in a state insulated from the gate electrode.
本発明に於いては、トランスファゲートを多段にしたた
めに、トランスファトランジスタを通過するリーク電流
を激減させることができる。つまりＰＮ接合の数が多く
なるので、接合１個当たりにかかる電圧が低下してリー
ク電流を下げるのである。しかも接合１個当たりのリー
ク電流は、その接合にかかる電圧が低くなると指数函数
的に減少する。In the present invention, since the transfer gate is provided in multiple stages, the leakage current passing through the transfer transistor can be drastically reduced. In other words, since the number of PN junctions increases, the voltage applied to each junction decreases, reducing leakage current. Moreover, the leakage current per junction decreases exponentially as the voltage applied to that junction decreases.
一方、本発明のＤＲＡＭの構造では、多段のトランスフ
ァゲートはトレンチの内部に形成されるので、トランス
ファゲートを多段にする事によってＤＲＡＭセルの占有
面積の増大を招（事がない。On the other hand, in the DRAM structure of the present invention, the multi-stage transfer gates are formed inside the trench, so the multi-stage transfer gates do not increase the occupied area of the DRAM cell.
大施班上
第１図Ａ−Ｆにより、本発明のＤＲＡＭの第１の実施例
をその製造方法の工程に基づいて説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of a DRAM of the present invention will be described based on the steps of its manufacturing method with reference to FIGS. 1A to 1F.
Ａ Ｉ”Ｓｉｉ板１板面表面ォトレジストのマスクパ
ターンを形成し、ＲＩＥ法によりトレンチ３を形成する
。これにより基板１表面には島状に形成された複数の柱
状突起４が形成される。A photoresist mask pattern is formed on the surface of the A I"Sii board 1, and trenches 3 are formed by RIE. As a result, a plurality of island-like columnar projections 4 are formed on the surface of the substrate 1.
アクセプターをトレンチの底にイオン注入して、チャン
ネルストッパー２を形成する。An acceptor is ion-implanted into the bottom of the trench to form a channel stopper 2.
Ｂ 熱酸化により第１ゲート酸化膜６を全面に形成する
。その後、第１多結晶Ｓｉ層５を成長させ、エッチバッ
クを行ってトレンチの下半分にキャパシタプレートを形
成する。B. A first gate oxide film 6 is formed over the entire surface by thermal oxidation. Thereafter, a first polycrystalline Si layer 5 is grown and etched back to form a capacitor plate in the lower half of the trench.
Ｃ，Ｄ柱状突起４の頂部からＲＩＥ法により深さ１．５
μのトレンチ７を形成する。形成されたトレンチ７を上
から見た状態がＤ図に示されている。Ｄ図のＣ−Ｃ線の
断面図が０図である。C, D Depth 1.5 from the top of columnar projection 4 by RIE method
A trench 7 of μ is formed. FIG. D shows the formed trench 7 viewed from above. 0 is a cross-sectional view taken along line C-C in figure D.
Ｅ 第２ゲート酸化膜８を形成した後、ドナーをイオン
注入してＳ／Ｄ領域９を形成する。その後第２多結晶Ｓ
ｉ［１０を成長させて、柱状突起部の中心部分を窓開け
する。E After forming the second gate oxide film 8, donor ions are implanted to form the S/D region 9. Then the second polycrystalline S
i[10 is grown and a window is opened in the center of the columnar projection.
Ｆ 層間絶縁膜１１を設けた後、ビット線コンタクト用
の窓を開け、／ｕ５ｔ１！線を行ってビット線１２を形
成する。F After providing the interlayer insulating film 11, open a window for bit line contact and /u5t1! A bit line 12 is formed by forming a bit line 12.
去旌開↓
ＡＰ−基板１上に、０．５μ厚のＮ３層、１μ厚のＰ一
層、０．５μ厚のＮ″層、１．５μ厚のＰ一層を各々エ
ピタキシャル成長させる。Opening↓ On the AP-substrate 1, a 0.5μ thick N3 layer, a 1μ thick P single layer, a 0.5μ thick N″ layer, and a 1.5μ thick P single layer are epitaxially grown.
Ｂ ＲＩＥ法によりトレンチを形成して、８μの高さ
の柱状突起部を形成し、その表面に熱酸化膜６を１５０
人成長させて第１ゲート酸化膜６とする。その後第１多
結晶５ｉｌｉ５を形成させてから、それのエッチバンク
を行い、キャパシタプレートを形成する。A trench is formed by the B RIE method to form a columnar protrusion with a height of 8μ, and a thermal oxide film 6 is deposited on the surface of the columnar protrusion with a thickness of 150 μm.
This is grown to form the first gate oxide film 6. Thereafter, a first polycrystal 5ili5 is formed, and then an etch bank is performed thereon to form a capacitor plate.
Ｃドナーをイオン注入して、柱状突起部の頂部にＮ″領
域形成する。第１ゲート酸化膜６をエツチング除去して
、第２ゲート酸化膜８を形成する。その後第２多結晶５
ｉ５１０を全面に形成する。A C donor is ion-implanted to form an N'' region at the top of the columnar protrusion. The first gate oxide film 6 is removed by etching to form a second gate oxide film 8. Thereafter, a second polycrystalline 5 is formed.
i510 is formed on the entire surface.
Ｄ 層間絶縁膜１１を形成し、層間絶縁膜１１、第２多
結晶Ｓｉ層１０及び第２ゲート酸化膜８をエッチする。D. An interlayer insulating film 11 is formed, and the interlayer insulating film 11, second polycrystalline Si layer 10, and second gate oxide film 8 are etched.
次いで酸化処理を行ってから、ＲＩＥ法を行いコンタク
ト窓の側壁を絶縁する。Next, an oxidation treatment is performed, and then an RIE method is performed to insulate the side walls of the contact window.
Ｅ Ａｔを全面に付着させ、パターニングを行ってビ
ット線１２を形成する。E At is deposited on the entire surface and patterned to form the bit line 12.
この実施例では、エピタキシャル法によりＰ一層とＮ″
層を積層させたが、ＰＳＧ膜をデポして、エッチバック
により柱状突起部にリング状に拡散層を設けることも可
能である。In this example, one layer of P and one layer of N'' are formed by epitaxial method.
Although the layers were laminated, it is also possible to deposit a PSG film and etch back to provide a ring-shaped diffusion layer on the columnar protrusion.
本発明の構造のＤＲＡ？ｌを採用することにより、トレ
ンチキャパシタからトランスフプトランジスタを通過し
てリークする電荷の量を大幅に減少させることができる
。DRA of the structure of the present invention? By employing 1, the amount of charge leaking from the trench capacitor through the transfer transistor can be significantly reduced.
また、多段に重ねられたトランスファゲートは、柱状突
起部内に形成されるので、そのメモリセルの面積が従来
のトレンチキャパシタ型ＤＲＡＭのメモリセルより大き
くなることはない。Furthermore, since the multi-stage transfer gates are formed within the columnar protrusion, the area of the memory cell does not become larger than that of a memory cell of a conventional trench capacitor type DRAM.
第１図Ａ−Ｆは本発明のＤＲＡＭの製造工程を示した図
である。
第２図Ａ−Ｅは、本発明のＤＲＡＭの他の実施例を示す
図である。
第３図は従来のトレンチキャパシタを示す図である。FIGS. 1A to 1F are diagrams showing the manufacturing process of the DRAM of the present invention. FIGS. 2A to 2E are diagrams showing other embodiments of the DRAM of the present invention. FIG. 3 is a diagram showing a conventional trench capacitor.
Claims (1)
電体層を介し、且つ先端を所定長さ残してキャパシタ電
極が形成され、前記の所定長さ残された先端部の表面に
ゲート絶縁膜を介し、且つ前記キャパシタ電極と絶縁さ
れてスイッチングトランジスタのゲート電極が形成され
、前記ゲート電極は前記複数の島状の突起部を所定方向
に結んで複数本形成され、前記複数の島状の突起部先端
部を中心にして前記スイッチングトランジスタを複数段
に分割する不純物領域が、前記突起部表面に形成され、
前記突起部先端部を所定方向に接続する複数の配線層が
、前記ゲート電極と絶縁されて形成されているメモリ装
置。A capacitor electrode is formed on the side wall of a plurality of island-like protrusions formed on a semiconductor substrate via a dielectric layer, leaving a predetermined length at the tip, and a gate insulator is formed on the surface of the tip with a predetermined length left. A gate electrode of a switching transistor is formed insulated from the capacitor electrode through a film, and a plurality of gate electrodes are formed by connecting the plurality of island-shaped protrusions in a predetermined direction, and the plurality of island-shaped protrusions are connected to each other in a predetermined direction. an impurity region dividing the switching transistor into a plurality of stages around a tip of the protrusion is formed on the surface of the protrusion;
A memory device in which a plurality of wiring layers connecting the tips of the projections in a predetermined direction are formed to be insulated from the gate electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61240574A JPS6394668A (en) | 1986-10-09 | 1986-10-09 | Storage device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61240574A JPS6394668A (en) | 1986-10-09 | 1986-10-09 | Storage device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6394668A true JPS6394668A (en) | 1988-04-25 |
Family
ID=17061546
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61240574A Pending JPS6394668A (en) | 1986-10-09 | 1986-10-09 | Storage device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6394668A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100585178B1 (en) | 2005-02-05 | 2006-05-30 | 삼성전자주식회사 | Semiconductor device comprising finfet having metal gate electrode and fabricating method thereof |
| US7279774B2 (en) | 2004-02-13 | 2007-10-09 | Samsung Electronics Co., Ltd. | Bulk substrates in FinFETs with trench insulation surrounding FIN pairs having FINs separated by recess hole shallower than trench |
-
1986
- 1986-10-09 JP JP61240574A patent/JPS6394668A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7279774B2 (en) | 2004-02-13 | 2007-10-09 | Samsung Electronics Co., Ltd. | Bulk substrates in FinFETs with trench insulation surrounding FIN pairs having FINs separated by recess hole shallower than trench |
| KR100585178B1 (en) | 2005-02-05 | 2006-05-30 | 삼성전자주식회사 | Semiconductor device comprising finfet having metal gate electrode and fabricating method thereof |
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