JPS6393278A - Focus detector - Google Patents

Focus detector

Info

Publication number
JPS6393278A
JPS6393278A JP61239784A JP23978486A JPS6393278A JP S6393278 A JPS6393278 A JP S6393278A JP 61239784 A JP61239784 A JP 61239784A JP 23978486 A JP23978486 A JP 23978486A JP S6393278 A JPS6393278 A JP S6393278A
Authority
JP
Japan
Prior art keywords
circuit
difference
output
delay
focus
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP61239784A
Other languages
Japanese (ja)
Inventor
Akihiro Fujiwara
昭広 藤原
Masamichi Toyama
当山 正道
Koichi Ueda
浩市 上田
Hiroshi Suda
浩史 須田
Kunihiko Yamada
邦彦 山田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Inc filed Critical Canon Inc
Priority to JP61239784A priority Critical patent/JPS6393278A/en
Publication of JPS6393278A publication Critical patent/JPS6393278A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N23/00Cameras or camera modules comprising electronic image sensors; Control thereof
    • H04N23/60Control of cameras or camera modules
    • H04N23/67Focus control based on electronic image sensor signals

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Automatic Focus Adjustment (AREA)
  • Focusing (AREA)

Abstract

PURPOSE:To obtain a high accuracy in terms of focusing decision with a simple constitution by permitting a 1st subtractor circuit to obtain the amplitude difference between picture signals on the boundary of an object, a 2nd subtractor circuit to obtain the gradient of the picture signal on said boundary and a comparator circuit to compare both values. CONSTITUTION:A difference circuit 36 calculates the difference between an I (N) from an image pickup element 30 and an I (N-2L-1) from a delay circuit 33. An output from a difference circuit 36 corresponds to the amplitude difference I between brightness and that two L later. A difference circuit 38 calculates the difference between an I (N-L-1) from a delay circuit 32 and an I (N-L) from a delay circuit 31. An output from the difference circuit 38 corresponds to a gradient dI/dx at a point N-L. An output from the difference circuit 36 is impressed on comparator circuits 42 and 44, and it is inspected whether it has magnification large enough to evaluate focusing. Parallel outputs from comparator circuits 46-52 are signals showing whether the optical system of the image pickup element 30 is focused or not. A decoder 55 decodes said signals into ones showing a focused state.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 有するカメラの合焦検出装置に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a focus detection device for a camera.

〔従来の技術とその問題点〕[Conventional technology and its problems]

ビデオ・カメラ等の電子撮像装置を有するカメラでは、
撮像素子から得られる画像信号を信号処理して映像の鮮
鋭度を検出することによりその合焦状態を検出・判定す
る方式が知られている。画像の鮮鋭度は、画像信号の高
周波成分の大小で評価できるが、被写体の種類やコント
ラストによって大きく変動するため、高周波成分の振幅
の絶対比較では的確な合焦検出はできなかった。即ち、
この変動を回避するために、合焦用レンズを光軸方向に
微小振動させて合焦評価値を相対化する工夫がなされた
が、この方法では、常に合焦用レンズを振動・変位させ
なければならず、モータ作動音、電力消費、合焦時の画
質劣化等の点で好ましいものではなかった。
For cameras with electronic imaging devices such as video cameras,
A method is known in which the in-focus state is detected and determined by signal processing an image signal obtained from an image sensor and detecting the sharpness of the image. Image sharpness can be evaluated by the magnitude of the high-frequency components of the image signal, but since it varies greatly depending on the type and contrast of the subject, it has not been possible to accurately detect focus by comparing the absolute amplitudes of the high-frequency components. That is,
In order to avoid this fluctuation, a method was devised to make the focusing lens vibrate minutely in the optical axis direction to relativize the focus evaluation value, but this method requires constant vibration and displacement of the focusing lens. However, it is not preferable in terms of motor operating noise, power consumption, image quality deterioration during focusing, etc.

これに対して、多くの被写体に共通して現れる人物や物
体の輪郭が画像信号では時間的に急激に変化する波形と
して現れることに注目し、その変化部分の明るさ勾配と
明るさの変化量との比を計算し、その比の大小で合焦状
態を検出・判断する方式が捉案された。この方式は、1
つのフィールド又はフレームで合焦状態を判定するので
、合焦用レンズを振動・変位させなくても合焦検出を行
いうるという利点がある。
On the other hand, we focused on the fact that the contours of people and objects, which commonly appear in many subjects, appear in image signals as waveforms that change rapidly over time. A method has been proposed in which the ratio between the two images is calculated and the in-focus state is detected and determined based on the magnitude of the ratio. This method is 1
Since the focus state is determined using one field or frame, there is an advantage that focus detection can be performed without vibrating or displacing the focusing lens.

この方式を簡単に説明すると、被写体(又は画面中の合
焦判定領域)が第3図(a)に示すような境界を有する
とすると、撮像素子から得られる画像信号1  (x)
は、光学系が合焦状態のときには第3図(blのように
鋭い変化を示すが、非合焦状態では第3図(C)のよう
になだらかな変化を示し、合焦状態から離れる程緩やか
に変化する。画像信号I(x)の変化部分の幅ΔXは、
合焦状態で最も小さい値Δx0になり、合焦状態から外
れるほど大きくなる。Δx0は被写体によらずほぼ一定
である。ΔX#Δx0ならば合焦状態であり、ΔX〉Δ
x0ならば非合焦状態と判定でき、この判定は、被写体
境界部分の平均明るさやコントラストに依らない。
To briefly explain this method, if the subject (or the focus judgment area on the screen) has a boundary as shown in Figure 3(a), the image signal 1 (x) obtained from the image sensor
When the optical system is in focus, it shows a sharp change as shown in Figure 3 (bl), but when it is out of focus, it shows a gentle change as shown in Figure 3 (C), and as it moves away from the focus state, The width ΔX of the changing portion of the image signal I(x) is
The smallest value Δx0 is obtained in the focused state, and increases as the value deviates from the focused state. Δx0 is approximately constant regardless of the subject. If ΔX#Δx0, it is in focus, and ΔX>Δ
If x0, it can be determined that the object is out of focus, and this determination does not depend on the average brightness or contrast of the object boundary.

従来の構成では、画像信号1  (x)の変化部分の勾
配d I / d xと、変化部分の振幅ΔIとを求め
、その比 P= (d I/d x)/ΔI を計算して、このΔXを表す値を得ていた。その構成例
を第4図に示す。
In the conventional configuration, the gradient d I / d x of the changing part of the image signal 1 (x) and the amplitude ΔI of the changing part are calculated, and the ratio P= (d I / d x) / ΔI is calculated. A value representing this ΔX was obtained. An example of its configuration is shown in FIG.

第4図において、撮像素子10から得られた画像信号I
  (x)は、微分回路(又は差分回路)12で微分さ
れ、そのd I / d xは絶対値回路14で正信号
にされる。積分回路16で の積分によりΔI  (x)を求め、対数圧縮回路18
で対数圧縮する。他方、遅延回路20は、dl/dxの
絶対値を積分回路16による時間遅延量に相応する時間
だけ遅延させ、対数圧縮回路22は遅延回路20の出力
を対数圧縮する。この対数圧縮により、除算の代わりに
減算で済む。差分回路24が対数回路18と対数回路2
2の出力を減算し、logP(x)を出力する。そして
、比較回路26が、差分回路24の出力と合焦判定閾値
1ogp0とを比較し、合焦判定を行う。
In FIG. 4, an image signal I obtained from the image sensor 10
(x) is differentiated by a differentiation circuit (or difference circuit) 12, and its dI/dx is made into a positive signal by an absolute value circuit 14. ΔI (x) is obtained by integration in the integration circuit 16, and the logarithmic compression circuit 18
Logarithmically compressed. On the other hand, the delay circuit 20 delays the absolute value of dl/dx by a time corresponding to the amount of time delay by the integrating circuit 16, and the logarithmic compression circuit 22 logarithmically compresses the output of the delay circuit 20. This logarithmic compression allows subtraction to be performed instead of division. The difference circuit 24 is a logarithm circuit 18 and a logarithm circuit 2.
Subtract the output of 2 and output logP(x). Then, the comparison circuit 26 compares the output of the difference circuit 24 and the focus determination threshold value 1ogp0 to determine focus.

この回路構成は、対数圧縮回路や積分回路という、それ
自体あまり精度の良くない回路要素を必要とするため、
合焦判定に許容される判定時間を考えると、高い合焦判
定精度をうるのは困難であった。更には、この構成は、
実際の設計・製造に際してインダクタや大容量のコンデ
ンサ等の半導体集積化に向かない回路素子を多く含み、
MOSやCCD型の撮像素子及び/又はその駆動制御回
路との集積化には適していない。
This circuit configuration requires circuit elements such as a logarithmic compression circuit and an integration circuit, which themselves are not very accurate.
Considering the determination time allowed for focus determination, it has been difficult to obtain high focus determination accuracy. Furthermore, this configuration
During actual design and manufacturing, many circuit elements such as inductors and large-capacity capacitors are not suitable for semiconductor integration.
It is not suitable for integration with a MOS or CCD type image sensor and/or its drive control circuit.

■提示t″″−h″1′。的6す6・     j!、
−F、へ本発明の第2の目的は、集積化に適したき無検
出装置を提示することである。
■Presentation t″″−h″1′. Target 6s6・j!,
-F. A second object of the present invention is to provide a non-detection device suitable for integration.

れた被写体像の情報を電気信号に変換する撮像素子から
の画像信号をそれぞれ所定時間遅延させる第1、第2、
第3の遅延回路と、当該撮像素子からの画像信号と第1
の遅延回路の出力との差値を出力する第1の減算回路と
、第2の遅延回路の出力と第3の遅延回路の出力との差
値を出力する第2の減算回路と、第1の減算回路の出力
と第2の減算回路の出力とを比較する比較回路とからな
り、当該比較回路による比較結果が当該被写体像の合焦
状態を示す。
first, second, and
a third delay circuit, an image signal from the image sensor and a first delay circuit;
a first subtraction circuit that outputs a difference value between the output of the second delay circuit and the output of the third delay circuit; and a comparison circuit that compares the output of the second subtraction circuit with the output of the second subtraction circuit, and the comparison result by the comparison circuit indicates the in-focus state of the subject image.

〔作用〕[Effect]

本発明では、上記第1の減算回路により被写体像の境界
部分の、画像信号の振幅差を求め、上記第2の減算回路
により当該境界部分の、画像信号の勾配を求める。そし
て、上記比較回路により両値を比較して被写体境界部分
の画像信号の鮮鋭度を判定する。このように各構成回路
が上記合焦検出の基本原理を忠実に実現しているので、
合焦検出の精度及び確度が高くなる。また、集積化し易
い回路構成となっているので、合焦検出回路全体の集積
化や、撮像素子と一体化しての集積化が可能となる。
In the present invention, the first subtraction circuit calculates the amplitude difference of the image signal at the boundary of the subject image, and the second subtraction circuit calculates the gradient of the image signal at the boundary. The comparison circuit then compares both values to determine the sharpness of the image signal at the object boundary. In this way, each component circuit faithfully realizes the basic principle of focus detection described above, so
The precision and accuracy of focus detection is increased. Furthermore, since the circuit configuration is easy to integrate, it is possible to integrate the entire focus detection circuit or integrate it with the image pickup device.

〔実施例〕〔Example〕

以下、図面を参照して、本発明の一実施例を説明する。 Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

第1図は、本発明の一実施例のブロック図を示す。MO
S型とかCCD型の撮像素子3oが画像信号Iを、I 
 (N−2L−1)、I  (N−2L)。
FIG. 1 shows a block diagram of one embodiment of the invention. M.O.
An S-type or CCD-type image sensor 3o receives an image signal I,
(N-2L-1), I (N-2L).

1  (N−L−1)、I  (N−L)、−、I  
(N−1)、1  (N)というように時系列的に出力
しているとする。遅延回路31,32.33は、それぞ
れり、L+1,2L+1の遅延時間に設定されており、
従って、撮像素子30からの原(87I(N)と同時に
、I  (N−L)、t (N−L−1)、I  (N
−2L−1)の信号が得られる。駆動回路40は、撮像
素子30を駆動すると共に、遅延回路31,32.33
も駆動し、撮像素子30の画像信号の続出タイミングと
遅延回路31゜32.33の遅延タイミングを同期させ
る。
1 (N-L-1), I (N-L), -, I
(N-1), 1 (N), etc. are output in chronological order. The delay circuits 31, 32, and 33 are set to delay times of L+1 and 2L+1, respectively.
Therefore, at the same time as the original (87I(N)) from the image sensor 30, I (N-L), t (N-L-1), I (N
-2L-1) signal is obtained. The drive circuit 40 drives the image sensor 30 and also controls the delay circuits 31, 32, and 33.
is also driven to synchronize the successive output timing of image signals from the image sensor 30 and the delay timing of the delay circuits 31, 32, and 33.

差分回路36は、撮像素子30からのI  (N)と遅
延回路33からのI  (N−2L−1)との差分を計
算する。差分回路36の出力は、2L(第3図(C)の
ΔXに対応)の時間差における明るさの振幅差ΔIに相
応する。また、差分回路38は、遅延回路32からのT
  (N−L−1)と遅延回路31からのI  (N−
L)との差分を計算する。差分回路38の出力は、時点
N−Lにおける勾配d1 / d xに相応する。これ
らの信号の関係を第2図に図示した。尚、第2図は第3
図(bl、 (C)に対応している。
The difference circuit 36 calculates the difference between I (N) from the image sensor 30 and I (N-2L-1) from the delay circuit 33. The output of the difference circuit 36 corresponds to the brightness amplitude difference ΔI at a time difference of 2L (corresponding to ΔX in FIG. 3(C)). The difference circuit 38 also receives T from the delay circuit 32.
(N-L-1) and I (N-
Calculate the difference with L). The output of the difference circuit 38 corresponds to the slope d1/dx at the time NL. The relationship between these signals is illustrated in FIG. In addition, Figure 2 is
Corresponds to figure (bl, (C)).

差分回路36の出力は、比較回路42.44に印加され
、評価用として充分な大きさか否かが検査される。比較
回路42.44の別の入力には、それぞれその評価用の
定電圧VSH0とVSH−が印加されている。また、差
分回路36の出力Δ■は直列抵抗R1〜R5で分割され
、その分圧がそれぞれ比較回路46.48,50.52
に印加される。他方、差分回路38の出力d I / 
d xは、比較回路46〜52の別の入力に印加される
。各比較回路46〜52は、2つの入力のどちらが大き
いかに応じて、高(H)又は低(L)の信号を出力する
。従って、出力がH(又はL)からしく又はH)に変化
する比較回路46〜52を調べることにより、dI/d
xとΔIの比、従って前述のΔX対応値を知ることが出
来る。換言すれば、比較回路46〜52による並列出力
は、その撮像素子30の光学系の合焦状態を示す信号で
ある。かかる信号はデコーダ55により焦点調節状態を
示す信号に変換される。
The output of the difference circuit 36 is applied to comparison circuits 42 and 44 to check whether it is large enough for evaluation. Constant voltages VSH0 and VSH- for evaluation are applied to other inputs of the comparison circuits 42 and 44, respectively. Further, the output Δ■ of the differential circuit 36 is divided by series resistors R1 to R5, and the divided voltages are divided into the comparator circuits 46.48 and 50.52, respectively.
is applied to On the other hand, the output d I / of the differential circuit 38
dx is applied to another input of comparator circuits 46-52. Each comparison circuit 46 to 52 outputs a high (H) or low (L) signal depending on which of the two inputs is larger. Therefore, by checking the comparator circuits 46 to 52 whose outputs change from H (or L) to lower or H), dI/d
The ratio of x and ΔI, and therefore the corresponding value of ΔX mentioned above, can be known. In other words, the parallel outputs from the comparison circuits 46 to 52 are signals indicating the focused state of the optical system of the image sensor 30. This signal is converted by the decoder 55 into a signal indicating the focus adjustment state.

Lの値は、合焦検出に適した、適当な値に設定しておく
が、上記説明から分かるように、2Lは、合焦状態での
被写体像の境界部分の画像信号の変化幅Δx0に等しい
かそれより大きくなければならない。
The value of L is set to an appropriate value suitable for focus detection, but as can be seen from the above explanation, 2L is the change width Δx0 of the image signal at the boundary of the subject image in the focused state. Must be equal to or greater than.

遅延回路31,32.33は電荷結合素子(CCD)の
みならず、MOS −FETスイッチとコンデンサで構
成された、所謂B’BDや、サンプル・ホールド回路を
必要段数並べた回路でも実現出来る。また、遅延回路3
1,32.33は撮像素子30と同一周期の駆動信号に
よって駆動されており、同一の半導体基板上に形成する
のが容易である。更には、差分回路36.38や比較回
路42〜52は種々の集積回路で採用されているものと
同じであるから、これらも同一の半導体基板上に形成す
るのは容易である。
The delay circuits 31, 32, and 33 can be realized not only by charge-coupled devices (CCDs) but also by so-called B'BDs composed of MOS-FET switches and capacitors, or by circuits in which a required number of sample-and-hold circuits are arranged. In addition, the delay circuit 3
1, 32, and 33 are driven by drive signals having the same cycle as the image sensor 30, and can be easily formed on the same semiconductor substrate. Furthermore, since the differential circuits 36, 38 and comparison circuits 42-52 are the same as those employed in various integrated circuits, they can also be easily formed on the same semiconductor substrate.

遅延回路31,32.33の遅延量はそれぞれをtI+
  jz、tlとすると1.=12+1□とすることが
望ましい。即ち第2図を用いて説明すると、この条件は
勾配を検出する装置(図中N−L−N−L−1)を振幅
差ΔIを検出した位五のほぼ中央とすることに相当する
。これにより一層検出精度を向上させることができる。
The delay amounts of the delay circuits 31, 32, and 33 are each tI+
If jz and tl, then 1. It is desirable that =12+1□. That is, to explain using FIG. 2, this condition corresponds to setting the slope detecting device (N-L-N-L-1 in the figure) approximately at the center of the digit where the amplitude difference ΔI is detected. Thereby, detection accuracy can be further improved.

〔発明の効果〕〔Effect of the invention〕

以上の説明から容易に理解出来るように、本発明によれ
ば、合焦判定の基本原理を忠実に実現する回路構成であ
るので、確度が高く信頼性の高い合焦判定信号を得るこ
とが出来′る。また、個々の回路要素が集積化に適した
ものであり、合焦検出回路の集積回路化、更には固体盪
像素子を含めての集積回路化も可能となり、コスト、実
装、消費電力等の面で、極めて優れた効果を発揮する。
As can be easily understood from the above explanation, according to the present invention, since the circuit configuration faithfully realizes the basic principle of focus determination, it is possible to obtain a highly accurate and reliable focus determination signal. 'ru. In addition, individual circuit elements are suitable for integration, making it possible to integrate focus detection circuits and even solid-state image elements, reducing costs, implementation, power consumption, etc. It exhibits excellent effects on the surface.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は、本発明に係る合焦検出装置の一実施例のブロ
ック図、第2図は、その動作説明用の波形図、第3図は
、本発明の基本原理の説明図、第4図は、本発明と同じ
基本原理に基づ〈従来の回路構成例を示す図である。 lO〜1最像素子 12・・−微分回路 14−絶対値
回路 16−・−積分回路 18−・・対数圧縮回路2
0・・−遅延回路 22・一対数圧縮回路 24−・−
差分回路 26−比較回路 30・−過像素子31、 
32. 33−遅延回路 36.38−・−・差分回路
 42,44.46.48,50.52−・比較回路 
4〇−駆動回路 第3図
FIG. 1 is a block diagram of an embodiment of the focus detection device according to the present invention, FIG. 2 is a waveform diagram for explaining its operation, FIG. 3 is an explanatory diagram of the basic principle of the present invention, and FIG. The figure is a diagram showing an example of a conventional circuit configuration based on the same basic principle as the present invention. lO~1 most image element 12--differentiating circuit 14-absolute value circuit 16--integrating circuit 18--logarithmic compression circuit 2
0...-Delay circuit 22-One-log compression circuit 24--
Differential circuit 26-comparison circuit 30-overimage element 31,
32. 33-Delay circuit 36.38-...Differential circuit 42,44.46.48,50.52--Comparison circuit
40-Drive circuit diagram 3

Claims (3)

【特許請求の範囲】[Claims] (1)撮像面に形成された被写体像の情報を電気信号に
変換する撮像素子からの画像信号をそれぞれ所定時間遅
延させる第1、第2、第3の遅延回路と、当該撮像素子
からの画像信号と第1の遅延回路の出力との差値を出力
する第1の減算回路と、第2の遅延回路の出力と第3の
遅延回路の出力との差値を出力する第2の減算回路と、
第1の減算回路の出力と第2の減算回路の出力とを比較
することにより焦合状態を示す信号を出力する比較回路
とを具備することを特徴とする焦点検出装置。
(1) First, second, and third delay circuits that each delay an image signal from an image sensor for a predetermined period of time, converting information about a subject image formed on an image sensor into an electrical signal, and images from the image sensor. A first subtraction circuit that outputs a difference value between the signal and the output of the first delay circuit, and a second subtraction circuit that outputs a difference value between the output of the second delay circuit and the output of the third delay circuit. and,
A focus detection device comprising: a comparison circuit that outputs a signal indicating a focus state by comparing the output of the first subtraction circuit and the output of the second subtraction circuit.
(2)前記第1、第2、第3の遅延回路が、前記撮像素
子を駆動する駆動信号と同期して駆動される電荷結合素
子である特許請求の範囲第(1)項に記載の焦点検出装
置。
(2) The focus according to claim (1), wherein the first, second, and third delay circuits are charge-coupled devices driven in synchronization with a drive signal that drives the image sensor. Detection device.
(3)前記第1、第2、第3の遅延回路の遅延時間を夫
々t_1、t_2、t_3とした場合にt_1=t_2
+t_3を満たすことを特徴とする特許請求の範囲第(
1)項又は第(2)項に記載の焦点検出装置。
(3) When the delay times of the first, second, and third delay circuits are t_1, t_2, and t_3, respectively, t_1=t_2
Claim No. 3, characterized in that it satisfies +t_3
The focus detection device according to item 1) or item (2).
JP61239784A 1986-10-08 1986-10-08 Focus detector Pending JPS6393278A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61239784A JPS6393278A (en) 1986-10-08 1986-10-08 Focus detector

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61239784A JPS6393278A (en) 1986-10-08 1986-10-08 Focus detector

Publications (1)

Publication Number Publication Date
JPS6393278A true JPS6393278A (en) 1988-04-23

Family

ID=17049834

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61239784A Pending JPS6393278A (en) 1986-10-08 1986-10-08 Focus detector

Country Status (1)

Country Link
JP (1) JPS6393278A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0456320A2 (en) * 1990-05-11 1991-11-13 Koninklijke Philips Electronics N.V. Automatic focus control device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0456320A2 (en) * 1990-05-11 1991-11-13 Koninklijke Philips Electronics N.V. Automatic focus control device

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