JPS6393158A - Nonvolatile semiconductor storage device - Google Patents
Nonvolatile semiconductor storage deviceInfo
- Publication number
- JPS6393158A JPS6393158A JP61238385A JP23838586A JPS6393158A JP S6393158 A JPS6393158 A JP S6393158A JP 61238385 A JP61238385 A JP 61238385A JP 23838586 A JP23838586 A JP 23838586A JP S6393158 A JPS6393158 A JP S6393158A
- Authority
- JP
- Japan
- Prior art keywords
- floating
- junction
- dart
- floating gate
- control
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 7
- 230000015556 catabolic process Effects 0.000 claims abstract description 9
- 239000000969 carrier Substances 0.000 claims abstract description 8
- 230000008878 coupling Effects 0.000 claims abstract description 3
- 238000010168 coupling process Methods 0.000 claims abstract description 3
- 238000005859 coupling reaction Methods 0.000 claims abstract description 3
- 239000000758 substrate Substances 0.000 abstract description 7
- 239000002784 hot electron Substances 0.000 abstract description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 16
- 230000005684 electric field Effects 0.000 description 12
- 230000005641 tunneling Effects 0.000 description 10
- 235000012239 silicon dioxide Nutrition 0.000 description 8
- 239000000377 silicon dioxide Substances 0.000 description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 7
- 229920005591 polysilicon Polymers 0.000 description 7
- 239000010410 layer Substances 0.000 description 6
- 230000014759 maintenance of location Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 230000005689 Fowler Nordheim tunneling Effects 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
Landscapes
- Non-Volatile Memory (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の目的〕
（産業上の利用分野）
本発明は浮遊ダートに電子を蓄えることにょ）清報を記
憶し、該情報を電気的に消去可能な不揮発性半導体記憶
装置に関する。[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention is a non-volatile semiconductor memory that stores news (electrons are stored in floating dirt) and can electrically erase the information. Regarding equipment.
（従来の技術）
従来、電気的に消去を行なう不揮発性半導体記憶装置で
典型的なものＫは、第５図ないし第７図のようなものが
ある。(Prior Art) Conventionally, typical nonvolatile semiconductor memory devices K that perform electrical erasing are shown in FIGS. 5 to 7.
第５図（１９８１Ｐｒｏｃｅｅｄｉｎｇ ｏｆ Ｉｎｔ
ｅｒｎａｔｉｏｎａｌＲｅｌｌａｂｌ ｌ ｉｔｙ Ｐ
ｈｙｓｉｃｓ Ｐ、 １１〜１６参考）（っまシ国際信
頼性物理シンポジウム会報）において、１はソース、２
はドレイン、３は浮遊ダート、４は制！ゲート、５はダ
ート酸化膜、６はトンネル酸化膜である。この構造では
、浮遊）ｙ”−トｓに蓄えられた電子を電気的に抜くた
めに、制御ダート４を接地し、ドレイン２に高い正の電
圧を印加してトンネル酸化膜６を電子が流れるようにし
ている。この場合電子がトンネル酸化膜を通シ抜ける仕
゛組みはファウラー・ノルドハイムトンネリング（Ｆ−
Ｎ・トンネリング）である。Figure 5 (1981Proceeding of Int.
ernationalRellable lity P
physics P, 11-16) (Bulletin of the International Reliable Physics Symposium), 1 is the source, 2
is drain, 3 is floating dart, 4 is control! The gate, 5 is a dirt oxide film, and 6 is a tunnel oxide film. In this structure, in order to electrically remove the electrons stored in the floating )y"-tos, the control dart 4 is grounded and a high positive voltage is applied to the drain 2, so that electrons flow through the tunnel oxide film 6. In this case, the mechanism by which electrons pass through the tunnel oxide film is called Fowler-Nordheim tunneling (F-Nordheim tunneling).
N tunneling).
第６図（Ｔｅｃｈｎｉｃａｌ ｄｌｇｅｓｔ ｏｆ Ｉ
ＥＤＭ １９８４Ｐ、４８０〜４８３参考）（つまシ国
際電子素子会誌の予稿集）において１１は１層目ポリシ
リコン。Figure 6 (Technical dlgest of I
In EDM 1984P, 480-483 (reference) (Tsumashi International Society of Electronic Devices Journal Proceedings), 11 is the first layer of polysilicon.
１２は浮遊ダート、１３は消去グー）、Ｊ（は浮遊ゲー
トポリシリコン上面の凹凸である。この構造では、浮遊
ダート１２に蓄えられた電子を電気的に抜くためには、
１層目のポリシリコン１１ｆ。12 is a floating dart, 13 is an erase goo), and J (is an unevenness on the upper surface of the floating gate polysilicon. In this structure, in order to electrically extract the electrons stored in the floating dart 12,
First layer polysilicon 11f.
接地し、消去ｆ−１−１３ＶＣ高い正の電圧を印加する
ことＫより、浮遊ダート１２から消去ゲート１３へ電子
がフ１ウラ−・ノルドノ−イムトンネリングを起こすよ
うにしている。この構造の場合は浮遊ｒ−トポリシリコ
ンの上面の凹凸１４が電界の局所的な増加をもたらし、
電子のトンネリングを増進しているのが特徴である。By grounding and applying a high positive voltage to the erase f-1-13VC, electrons from the floating dart 12 to the erase gate 13 are caused to undergo fuller-norm tunneling. In this structure, the irregularities 14 on the top surface of the floating r-polysilicon cause a local increase in the electric field;
It is characterized by enhanced electron tunneling.
第７図（Ｔｅｃｈｎｉｃａｌ ｄＩｇｅｓｔ ｏｆ Ｉ
Ｂ Ｄ Ｍ１９８５ Ｐ、６１６〜６１９）におい
て、２１はソース、２２はドレイン、２３は浮遊ｒ−ト
。Figure 7 (Technical dIgest of I
BD M1985 P, 616-619), 21 is a source, 22 is a drain, and 23 is a floating r-t.
２４は消去ダートを兼ねた制御ｆ−ト、２５は基板であ
る。この構造では、浮遊ｒ−ト２３に蓄えられた電子を
電気的に抜くためにソース２１．ドレイン２２．基板２
５を接地し、消去ダートを兼ねた制御ゲート２４に高い
正の電圧を印加することＫよシ、浮遊ｒ−ト２３から消
去ｒ−ト２４へ電子がフ１ウラ−・ノルドハイムトンネ
リングを起こす。Reference numeral 24 represents a control f-tar which also serves as an erase dart, and 25 represents a substrate. In this structure, the source 21. Drain 22. Board 2
5 is grounded and a high positive voltage is applied to the control gate 24, which also serves as an erase dart, to cause electrons to undergo floating-nordheim tunneling from the floating gate 23 to the erase gate 24. .
（発明が解決しようとする問題点）
以上の３例とも、電気的に電子を抜くために電子のフ１
ウラ−・ノルドハイムトンネリング（参考、 Ｊｏｕｒ
ｎａｌ ｏｆ Ａｐｐｌｉｅｄ Ｐｈｙｓｌｃｓ Ｖｏ
１４０゜Ｐ、２７８〜２８３ （１９６９））を用いて
いるが、このメカニズムで電子が二酸化シリコンを流れ
るためには、かな）大きな電界を加えなければならない
。（６〜７ＭＶ／ｃ７！Ｌ以上）このため第５図の例で
は非常に薄いトンネル用の二酸化シリコン膜を形成する
が、非常に薄い二酸化シリコン膜は形成が困難で信頼性
にも問題がある。(Problems to be solved by the invention) In all of the above three examples, an electron beam is used to electrically extract electrons.
Ulla-Nordheim Tunneling (Reference, Jour
nal of Applied Physlcs Vo
140°P, 278-283 (1969)), but in order for electrons to flow through silicon dioxide using this mechanism, a large electric field must be applied. (6 to 7 MV/c7!L or more) Therefore, in the example shown in Figure 5, a very thin silicon dioxide film is formed for the tunnel, but it is difficult to form a very thin silicon dioxide film and there are problems with reliability. .
電子のトンネリングが起きるために印加しなければなら
ない電界（電圧）を低減するために、第６図、第７図の
例では浮遊ダートポリシリコン上面の凹凸による電界の
局所的な増加を用いている。In order to reduce the electric field (voltage) that must be applied for electron tunneling to occur, the examples in Figures 6 and 7 use a local increase in the electric field due to the irregularities on the top surface of the floating dirt polysilicon. .
これ以外にも、シリコンを多く含む二酸化シリコンを浮
遊ダートの間の絶縁膜に用いることによってもトンネリ
ングに必要な電界を下げることができる。（参考、 Ｊ
ｏｕｒｎａｌ ｏｆ ＡｐｐｌＩｅｄ Ｐｈｙｓｌｃｓ
５．４ 、Ｐ ５８０１〜５８２７ （１９８３））し
かし、上の２つの方法は浮遊ｒ−）Ｋ蓄えられている電
子の保持を悪くする（情報を消したくない場合に情報が
消えやすい）傾向があるので、ポリシリコン上面の凹凸
の程度や二酸化シリコン中の余分のシリコンの量のコン
トロールが微妙になるという欠点がある。In addition to this, the electric field required for tunneling can also be lowered by using silicon dioxide containing a large amount of silicon as an insulating film between floating darts. (Reference, J.
Our own of ApplIed Physlcs
5.4, P. 5801-5827 (1983)) However, the above two methods tend to deteriorate the retention of floating r-)K stored electrons (information tends to disappear when it is not desired to erase it). Therefore, there is a drawback that the degree of unevenness on the top surface of polysilicon and the amount of excess silicon in silicon dioxide are delicately controlled.
本発明は上記実情に鑑みてなされたもので、高電界を印
加しないでも浮遊ダートに蓄えられた電子を抜くことが
でき、信頼性が向上する不揮発性半導体記憶装置を提供
することを目的とする。The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a nonvolatile semiconductor memory device that can extract electrons stored in floating dirt without applying a high electric field, and has improved reliability. .
（問題点を解決するための手段と作用）本発明は、浮遊
ゲートＫよ！ｌｌ情報を記憶する不揮発生半導体記憶装
置において、浮遊ダート内ＫＰＮ接合を形成し、容量に
よる結合でこのＰＮ接合の電位をコントロールしシ
シ
てアバランノエプレークダウンを起こし、それにより生
じたホットキャリアを浮遊ダートの外へ引き抜くことに
より消去を行彦うようＫしたものである。(Means and effects for solving the problems) The present invention is a floating gate K! In a nonvolatile semiconductor memory device that stores information, a KPN junction is formed in the floating dirt, and the potential of this PN junction is controlled by capacitive coupling to cause avalanche leakdown, and the resulting hot carriers are suspended. It is designed so that it can be erased by pulling it out of the dirt.
（実施例）
以下図面を参照して本発明の一実施例を説明する。はじ
めに、二酸化シリコン中を電子が伝導ランシェ注入は低
電界でも伝導が非常に起こ夛やすく、抵抗のオーダが何
桁も異なることは知られており、電界による抵抗率を比
較したものを第４図に引用しておく。（引用文献 Ｈ，
Ｃ，Ｃｏｒｄ ａｎｄＭ、ｉＪ３１ｍａｓｒｙ ｒｐｕ
ｒｃ口ａｎａｌ Ｍｏｄｅｌｌｉｎｇ ｏｆ Ｎｏｎ−
Ｖｏｌａｔｌｌｅ ＭＯＳ ｍｅｍｏｒｙ ｄｅｖｉｃ
ｅｓ Ｊ ５ｏｌｉｄ−８ｔａｔｅＥｌｅｃｔｒｏｎｉ
ｃｓ Ｖｏｌ １９ Ｐ、８６３〜８７０ （１９７６
） ）第１図は本実施例の断面図、第２図は第１図の■
−…線に沿う断面図である。図中３１は浮遊ダートのＮ
型部、３２は浮遊ダート上の１番目の制御ダート、３３
は基板、３４は浮遊ダートのＰ型部、３５はゲート側方
の２番目の制御ｙ−）１゜３６はソース層、３７はドレ
イン層、３８は絶縁膜でらシ、この構成の特徴は、浮遊
ダートにＰＮ接合を設けた点である。(Example) An example of the present invention will be described below with reference to the drawings. First, it is known that conduction of electrons in silicon dioxide is very easy to occur even in a low electric field during Lanche injection, and that the resistance differs by several orders of magnitude. Figure 4 shows a comparison of the resistivity due to the electric field. I will quote it. (Cited documents H,
C, Cord and M, iJ31masry rpu
rc mouth anal Modeling of Non-
Volatlle MOS memory device
es J 5solid-8tateElectroni
cs Vol 19 P, 863-870 (1976
)) Figure 1 is a cross-sectional view of this example, and Figure 2 is a cross-sectional view of Figure 1.
-... is a cross-sectional view along the line. 31 in the figure is floating dirt N
Mold part, 32 is the first control dart on the floating dart, 33
is the substrate, 34 is the P-type part of the floating dart, 35 is the second control on the side of the gate, 36 is the source layer, 37 is the drain layer, and 38 is the insulating film.The characteristics of this structure are , the floating dart is provided with a PN junction.
第１図、第２図において「書き込み」の場合は、ソース
３６と基板３３を接地し、制御ゲート３２と２番目の制
ｗＵダート３５とドレイン３７に正の高［王を印加し、
第２図に見られるＮチャネルＭＯ８型トランジスタのド
レインアバランシェ現象により生じたホットキャリアを
、浮遊グー）Ｋ注入を行なう点で従来例と同様である。In the case of "writing" in FIGS. 1 and 2, the source 36 and the substrate 33 are grounded, and a positive high voltage is applied to the control gate 32, the second control gate 35, and the drain 37.
This is similar to the conventional example in that hot carriers generated by the drain avalanche phenomenon of the N-channel MO8 type transistor shown in FIG. 2 are injected with floating K.
「消去」の場合は制御グー）３２に正の高電圧Ｖ、を印
加し２番目−の制御ｒ −） ３５を接地しておく。こ
の時、浮遊ゲートのＮ型部３１とＰ型部３４の電位がど
のようになるかを第３図をもとに考えてみる。ここでＶ
、は制御ダート３２に印加した電圧１ ■ＳＤＢはソー
ス３６．基板３３．ドレイン３７の電位だが、計算の簡
略化のためＯｖとする。Ｃｔ−ｔは浮遊ダートのＮ型部
３１と制御ダート３２間の容ｆｆｉ ＝ Ｃｔ−ｈは浮
遊ダートのＰＮ接合容８．Ｃ４−５は浮遊ダートのＰ型
部３４と第２の制御ダート３５間の容量、Ｃｌ−８ＤＢ
は浮遊ｒ−トとソース、ドレイン、基板の間容量とする
。浮遊ダートのＰ型部３４と制ｍｉｌ？”−）ｓｘ間の
容量はオーバーラツプが非常に小さいので無視する。制
御ｒ−ト３２と第２の制御ダート３５間の容量は層間膜
厚が厚いので無視する。簡単のため浮遊ダートの持つ電
荷を０とする。In the case of "erase", a positive high voltage V is applied to the control (r) 32, and the second control (r-) 35 is grounded. At this time, consider what the potentials of the N-type part 31 and the P-type part 34 of the floating gate will be based on FIG. Here V
, is the voltage 1 applied to the control dart 32. ■SDB is the voltage 1 applied to the control dart 32. Substrate 33. The potential of the drain 37 is set to Ov to simplify calculation. Ct-t is the capacitance between the N-type part 31 of the floating dart and the control dart 32ffi=Ct-h is the PN junction capacitance of the floating dart8. C4-5 is the capacitance between the P-type part 34 of the floating dart and the second control dart 35, Cl-8DB
is the capacitance between the floating r-t and the source, drain, and substrate. Floating dart P type part 34 and control mil? ``-)sx is ignored because the overlap is very small.The capacitance between the control dart 32 and the second control dart 35 is ignored because the interlayer film thickness is thick.For simplicity, the charge held by the floating dart is Let be 0.
浮遊ダートのＮ型部３１の電位ｖ８は
ただしく１）弐においてにとなるためＫは、セルの条件
゛をＣ１−４＜＜ Ｃｔ−＊ ｓ Ｃ１−４＜（Ｃま
−、とする。また浮遊ダートのＰ型部３４の電位ｖ４は
、ｚＯ・・・・・・・・・・・・・・・・・・・・・・
・・（２）ただしく２）式においてたとなるためには、
セルの条件をＣ１一番＜＜Ｃ４−１とし、浮遊ダートの
ＰＮ接合にはおよそ
の電位差が印加されることになる。通常Ｃ！−１はＣｌ
−８ＢＤ の数倍の値をとるので、ＰＮ接合にはｖｌの
大部分が加わる。よってＰＮ接合のブレークダウンを生
じさせることは不純物の度を調整することＫよシ十分可
能である。−担プレークダウンを生ずると０１−４はシ
ョートされた状態になり、浮遊ゲートの電位ｖ′は、Ｐ
Ｎ接合のブレークダウン電圧が充分低いとすれば、
に落ちつく。この時までにアバランシェで生じた電荷は
正、負おのおの
Ｑ”Ｃ４−１（Ｖ”−Ｖ４）
トナルｏ Ｃｔ−ｘ＝ Ｃ４−１＞ Ｃ１−５ＤＢ
Ｊ： ’） Ｑ＝Ｃ鵞−ｔ・ｖ、／２のオーダである。Since the potential v8 of the N-type part 31 of the floating dart is exactly 1), K sets the cell condition as C1-4<< Ct-*s C1-4<(C-). The potential v4 of the P-type part 34 of the floating dirt is zO...
...(2) However, in order to hold in equation 2),
The cell condition is set as C1<<C4-1, and an approximate potential difference is applied to the PN junction of the floating dart. Normally C! -1 is Cl
Since it takes a value several times as large as -8BD, most of vl is added to the PN junction. Therefore, it is possible to cause breakdown of the PN junction by adjusting the degree of impurity. - When the carrier breakdown occurs, 01-4 becomes short-circuited, and the potential v' of the floating gate becomes P
If the breakdown voltage of the N junction is low enough, it will settle to . By this time, the charges generated by the avalanche are positive and negative respectively Q"C4-1(V"-V4) Tonal o Ct-x= C4-1> C1-5DB
J: ') Q=C-t·v, of the order of /2.
アパランシェブレークダウンで生じたホットエレクトロ
ンのわずかな部分が制御１ｌｌＩダートへ抜けるので、
制御ｅ−）３２と第２の制御ゲート３５をまとめてダー
トと見なしたＭＯＳ ）ランジスタのしきい値電圧を十
分大きく変動させるためには高′ｆ！Ｌ田の印加と切断
をくり返してアパランシェブレークダウンを繰り返し発
生させることが必要になるだろう。（ホットホールは二
酸化シリコンの障壁が電子よシ高いので、電子の抜けと
くらべると無視できる）本実施例の場合、フ１ウラ−・
ノルドハイムトンネリングで電子を浮遊ダートから抜く
場合にくらべ、低電界で電子を浮遊ダートから抜くこと
ができるので使用′Ｊ１掠電圧電圧くでき、キャリアと
Ｋより、保持特性の向上も期待できる。A small portion of the hot electrons generated by the apalanche breakdown escapes to the control 1llI dirt, so
The control e-) 32 and the second control gate 35 are collectively regarded as a dart.) In order to vary the threshold voltage of the transistor sufficiently, the high 'f! It will be necessary to repeatedly apply and disconnect the L field to repeatedly generate aparanche breakdown. (Since the barrier of silicon dioxide is higher than that of electrons, hot holes can be ignored compared to the loss of electrons.) In the case of this example, hot holes
Compared to the case where electrons are extracted from floating darts by Nordheim tunneling, electrons can be extracted from floating darts with a lower electric field, so the voltage used can be lowered, and retention characteristics can be expected to be improved due to carriers and K.
なお本発明は実施例に限られず種々の応用が可能である
。例えば本実施例の製造プロセスは特に複雑な工程は用
いないが、できることならば浮遊ダートはポリシリコン
をレーデ−アニールする事によｆｉ、ＰＮ接合の特性を
バルクのＰＮ接合特性に近づけておくことが望ましい。Note that the present invention is not limited to the embodiments and can be applied in various ways. For example, the manufacturing process of this embodiment does not use particularly complicated steps, but if possible, the floating dirt should be removed by radar annealing the polysilicon, and the characteristics of the PN junction should be kept close to those of the bulk PN junction. is desirable.
また浮遊ダートのＰ型部の形成は制ｔｉｌｌ”−ト３２
をマスクにして行なうと、ホットキャリアの大量に生成
されるＰＮ接合部がわずかに制御ｎ” −） ｓ ２の
下にはいるため、ホットキャリアを引き抜く効率が良い
。In addition, the formation of a P-type part of floating dirt can be prevented.
When this is carried out using a mask, the PN junction where a large amount of hot carriers are generated is slightly under the control n''-)s2, so that hot carriers can be drawn out efficiently.
以上に述べたように、浮遊ダートに形成したＰＮ接合の
アパランシェブレークダウンをさせて生じたホットエレ
クトロンを抜くことＫよシ、情報の消去を行なうようＫ
したため、従来のフ１ウラ−・ノルドハイム・トンネリ
ングで電子を抜く方法にくらべて印加する電界を低くす
ることができ、電録電圧を低くでき、絶縁膜の信頼性を
上げることもできる。また従来の例のように絶縁膜のリ
ーク特性を悪く （リークを大きく）することはないの
で、保持特性（浮遊ｒ−トに蓄えられた電子の保持）Ｋ
は問題を生ずることなく、低電界で消去できる分だけ絶
縁膜厚を厚くすることにより保持特性を向上させること
も可能である。As mentioned above, in addition to extracting the hot electrons generated by aparanche breakdown of the PN junction formed in the floating dirt, it is also necessary to erase information.
Therefore, compared to the conventional method of extracting electrons using Fuller-Nordheim tunneling, the applied electric field can be lowered, the recording voltage can be lowered, and the reliability of the insulating film can be improved. In addition, unlike the conventional example, the leakage characteristics of the insulating film are not deteriorated (leakage is increased), so the retention characteristic (retention of electrons stored in floating r-t) is
It is also possible to improve the retention characteristics by increasing the thickness of the insulating film by the amount that can be erased with a low electric field without causing any problems.
第１図は本発明の一実施例を示す断面図、第２図は第１
図の■−■線に沿う断面図、第３図は同実施例の消去時
の電位を求めるための等価回路図、第４図は二酸化シリ
コン膜における電界強度と抵抗率の関係を示す特性図、
第５図ないし第７図は従来装置の断面図である。
３１・・・浮遊ダートのＮ型部、３２・・・制御ｒ−）
、３３・・・基板、３４・・・浮遊ゲートのＰ型部、３
５・・・２番目の制御ダート、３６・・・ソース層、３
７・・・ドレイン層、３８・・・絶縁膜。
出願人代理人弁理士 鈴 江 武 彦
■
第 １ 図
第２ 口
第３図
第４図FIG. 1 is a sectional view showing one embodiment of the present invention, and FIG.
3 is an equivalent circuit diagram for determining the potential during erasing in the same example, and FIG. 4 is a characteristic diagram showing the relationship between electric field strength and resistivity in the silicon dioxide film. ,
FIGS. 5 to 7 are cross-sectional views of conventional devices. 31... N-type part of floating dart, 32... Control r-)
, 33... Substrate, 34... P-type part of floating gate, 3
5...Second control dart, 36...Source layer, 3
7... Drain layer, 38... Insulating film. Patent attorney representing the applicant Takehiko Suzue■ Figure 1 Figure 2 Figure 3 Figure 4
Claims (1)
不揮発性半導体記憶装置において、前記浮遊ゲート内に
ＰＮ接合を形成し、容量による結合で前記ＰＮ接合の電
位をコントロールしてアパランシェブレークダウンを起
こし、それにより生じたホットキャリアを前記浮遊ゲー
トの外へ引き抜くことで消去を行なう手段を具備したこ
とを特徴とする不揮発性半導体記憶装置。In a nonvolatile semiconductor memory device that stores information by storing electrons in a floating gate, a PN junction is formed in the floating gate, and the potential of the PN junction is controlled by capacitive coupling to cause aparanche breakdown, 1. A nonvolatile semiconductor memory device comprising means for erasing by drawing hot carriers generated thereby out of the floating gate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61238385A JPS6393158A (en) | 1986-10-07 | 1986-10-07 | Nonvolatile semiconductor storage device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61238385A JPS6393158A (en) | 1986-10-07 | 1986-10-07 | Nonvolatile semiconductor storage device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6393158A true JPS6393158A (en) | 1988-04-23 |
Family
ID=17029405
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61238385A Pending JPS6393158A (en) | 1986-10-07 | 1986-10-07 | Nonvolatile semiconductor storage device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6393158A (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5095344A (en) * | 1988-06-08 | 1992-03-10 | Eliyahou Harari | Highly compact eprom and flash eeprom devices |
| US5168465A (en) * | 1988-06-08 | 1992-12-01 | Eliyahou Harari | Highly compact EPROM and flash EEPROM devices |
| US5554553A (en) * | 1988-06-08 | 1996-09-10 | Harari; Eliyahou | Highly compact EPROM and flash EEPROM devices |
| EP0740306A2 (en) * | 1991-01-31 | 1996-10-30 | Interuniversitair Microelektronica Centrum Vzw | Method of programming a semiconductor memory device |
| US5650649A (en) * | 1993-12-14 | 1997-07-22 | Nec Corporation | Floating gate type field effect transistor having control gate applied with pulses for evacuating carriers from p-type semiconductor floating gate |
| JP2009188291A (en) * | 2008-02-08 | 2009-08-20 | Nec Electronics Corp | Nonvolatile semiconductor storage and method of manufacturing method the same |
| JP2012049515A (en) * | 2010-07-28 | 2012-03-08 | Semiconductor Energy Lab Co Ltd | Semiconductor device and driving method of semiconductor device |
| EP2560195A1 (en) * | 2011-08-17 | 2013-02-20 | Hitachi, Ltd. | Memory device with an isolated gate comprising two portions separated by a barrier and method of operating the same |
-
1986
- 1986-10-07 JP JP61238385A patent/JPS6393158A/en active Pending
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5095344A (en) * | 1988-06-08 | 1992-03-10 | Eliyahou Harari | Highly compact eprom and flash eeprom devices |
| US5168465A (en) * | 1988-06-08 | 1992-12-01 | Eliyahou Harari | Highly compact EPROM and flash EEPROM devices |
| US5554553A (en) * | 1988-06-08 | 1996-09-10 | Harari; Eliyahou | Highly compact EPROM and flash EEPROM devices |
| EP0740306A2 (en) * | 1991-01-31 | 1996-10-30 | Interuniversitair Microelektronica Centrum Vzw | Method of programming a semiconductor memory device |
| EP0740306A3 (en) * | 1991-01-31 | 1996-11-13 | Interuniversitair Microelektronica Centrum Vzw | Method of programming a semiconductor memory device |
| US5650649A (en) * | 1993-12-14 | 1997-07-22 | Nec Corporation | Floating gate type field effect transistor having control gate applied with pulses for evacuating carriers from p-type semiconductor floating gate |
| JP2009188291A (en) * | 2008-02-08 | 2009-08-20 | Nec Electronics Corp | Nonvolatile semiconductor storage and method of manufacturing method the same |
| JP2012049515A (en) * | 2010-07-28 | 2012-03-08 | Semiconductor Energy Lab Co Ltd | Semiconductor device and driving method of semiconductor device |
| JP2016006878A (en) * | 2010-07-28 | 2016-01-14 | 株式会社半導体エネルギー研究所 | Semiconductor device |
| EP2560195A1 (en) * | 2011-08-17 | 2013-02-20 | Hitachi, Ltd. | Memory device with an isolated gate comprising two portions separated by a barrier and method of operating the same |
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