JPS639297A - Cyclic type noise reduction device - Google Patents
Cyclic type noise reduction deviceInfo
- Publication number
- JPS639297A JPS639297A JP61153033A JP15303386A JPS639297A JP S639297 A JPS639297 A JP S639297A JP 61153033 A JP61153033 A JP 61153033A JP 15303386 A JP15303386 A JP 15303386A JP S639297 A JPS639297 A JP S639297A
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- Prior art keywords
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- signal
- luminance
- noise reduction
- signals
- Prior art date
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- 125000004122 cyclic group Chemical group 0.000 title claims abstract description 39
- 238000006243 chemical reaction Methods 0.000 claims abstract description 44
- 230000003111 delayed effect Effects 0.000 claims description 4
- 238000000926 separation method Methods 0.000 abstract description 5
- 238000010586 diagram Methods 0.000 description 7
- 230000000694 effects Effects 0.000 description 7
- 238000000034 method Methods 0.000 description 5
- 230000006870 function Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000013459 approach Methods 0.000 description 1
- 239000000284 extract Substances 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
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- Processing Of Color Television Signals (AREA)
Abstract
Description
【発明の詳細な説明】
「産業上の利用分”ＩＦ ］
この発明は、輝度信号と色信号を時分割多重し、単一の
巡回型雑音低減回路により雑音低減するようにした巡回
型雑音低減装置に関する。Detailed Description of the Invention "Industrial Application" IF] This invention provides cyclic noise reduction in which luminance signals and chrominance signals are time-division multiplexed and the noise is reduced by a single cyclic noise reduction circuit. Regarding equipment.
［従来の技術］
家庭用に用いられるビデオテープレコーダ等の磁気記篠
′再生装置は、周波数変調した輝度信号に低域変換した
色信号を周波数多重して記録する構成をとるが、記録・
再生に関する信号処理過程で混入する雑音成分を取り除
く」二で、格別効果の高いものに巡回型雑音低減法があ
る。この巡回型雑音低減法は、フィールド周期成はフレ
ーム周期でもって高い信号相関を示す映像信号に固自の
性質に着目し、画像メモリにて１フイ一ルド期間又は１
フレ一ム期間遅延させた出力を入力に巡回的に加算する
ことにより、雑音を除去する方法である。[Prior Art] Magnetic recording and reproducing devices such as video tape recorders used for home use have a configuration in which frequency-modulated luminance signals are frequency-multiplexed and low-frequency converted color signals are recorded.
Cyclic noise reduction is an especially effective method for removing noise components mixed in during the signal processing process related to reproduction. This cyclic noise reduction method focuses on the unique property of video signals that show a high signal correlation with the field periodicity and the frame period.
This method removes noise by cyclically adding the output delayed by one frame period to the input.
第４図に示す従来の巡回型雑音低減装置１は、ビデオ信
号に含まれる輝度信号Ｙと色信号Ｃを、輝度・色分離回
路２にて分離したあと、色信号Ｃをデコード回路３にて
Ｒ−ＹとＢ−Ｙの２つの色差信号に分解する。その後、
各信号ごとに用意したＡＤ変換回路４，５．６により、
輝度信号Ｙ。The conventional cyclic noise reduction device 1 shown in FIG. It is decomposed into two color difference signals, RY and B-Y. after that,
By AD conversion circuits 4, 5.6 prepared for each signal,
Luminance signal Y.
色差信号Ｒ−Ｙ、Ｂ−Ｙをぞれぞれ別個にＡＤ変換し、
各ＡＤ変換回路４，５．６に接続した巡回型雑音低減回
路７，８．９にて雑音低減処理を施したのち、ＤＡ変換
回路１０．］、１．＋２にて各信号をＤＡ変換する。Ｄ
Ａ変換回路ＩＩ、１２の出力である色差信号Ｒ−Ｙ、Ｉ
（−Ｙはエンコード回路１３にて色信号Ｃに合成され、
輝度・色混合回路１４にてＤＡ変換回路１０の出力であ
る輝度信号Ｙに混合されて出力される。１５は、ＡＤ変
換回路４．５．６と巡回型雑音低減回路７，８゜９及び
ＤＡ変換回路１０，１１，１２のクロック信号を発生す
るクロック発生回路であり、変換対象となる映像信号中
の水平同期信号を分離し、分離した水平同期信号の周波
数ｆ ＋ｔの整数倍の周波数をもつクロック信号を形成
する。なお、本例に用いられるＡ Ｉ）変換回路４，５
．６とＤＡ変換回路１０，１１．＋２のクロック信号の
周波数は、４５６ ｆ Ｈ、＋ Ｉ ４ ｆ ｕ 、Ｉ
Ｉ ４ ｆ ｕであり、色副搬送周波数ｆ ｓ ｃ
（＝２２７．５ ｆ ｎ）の約２倍、１７２倍、１／２
倍の周波数に相当する。AD convert the color difference signals R-Y and B-Y separately,
After performing noise reduction processing in the cyclic noise reduction circuits 7, 8.9 connected to each AD conversion circuit 4, 5.6, the DA conversion circuit 10. ], 1. +2 performs DA conversion on each signal. D
The color difference signals R-Y, I which are the outputs of the A conversion circuits II and 12
(-Y is combined with the color signal C in the encoding circuit 13,
The luminance/color mixing circuit 14 mixes the signal with the luminance signal Y, which is the output of the DA conversion circuit 10, and outputs the mixed signal. 15 is a clock generation circuit that generates clock signals for the AD conversion circuit 4.5.6, the cyclic noise reduction circuits 7, 8゜9, and the DA conversion circuits 10, 11, and 12; A clock signal having a frequency that is an integral multiple of the frequency f + t of the separated horizontal synchronizing signal is formed. Note that the A I) conversion circuits 4 and 5 used in this example
．． 6 and DA conversion circuits 10, 11. The frequency of the +2 clock signal is 456 f H, + I 4 f u , I
I 4 f u and the color subcarrier frequency f sc
Approximately twice, 172 times, 1/2 of (=227.5 f n)
This corresponds to twice the frequency.
［発明が解決しようとする問題点１
上記従来の巡回型雑音低減装置１は、輝度信号Ｙと色差
信号Ｔ’ｌ−Ｙ、Ｂ−Ｙを並行してＡＤ変換する必要が
あるとはいえ、ＡＤ変換回路が４．５゜６の３個、ＤＡ
変換回路が１０，１１，１２の３個必要であり、さらに
実際トは輝度信号Ｙはどの厳密かつ広帯域の雑音低減処
理を必要としない色差信号Ｒ−Ｙ、Ｂ−Ｙにまで、独立
した雑音低減処理を施しているために、高価な画像メモ
リを用いる巡回型雑音低減回路が、７，８．９と３個も
必要であり、従って装置構成の複雑化と製造コストの増
大が避けられず、またＡＤ変換回路４に比較してＡＤ変
換回路５．６の変換能力に余裕が生じてしまうため、同
じ素子構成のものを用いた場合に、ＡＤ変換回路５．６
の変換能力を十分活用しきれない等の問題点があった。[Problem to be Solved by the Invention 1] Although the conventional cyclic noise reduction device 1 described above needs to perform AD conversion on the luminance signal Y and the color difference signals T'l-Y and B-Y in parallel, Three AD conversion circuits of 4.5°6, DA
Three conversion circuits 10, 11, and 12 are required, and in fact, the luminance signal Y has independent noise, even the color difference signals R-Y and B-Y, which do not require strict and broadband noise reduction processing. Because the reduction processing is performed, three cyclic noise reduction circuits (7, 8, and 9) using expensive image memory are required, which inevitably complicates the device configuration and increases manufacturing costs. In addition, since there is a margin in the conversion capability of the AD conversion circuit 5.6 compared to the AD conversion circuit 4, when using the same element configuration, the AD conversion circuit 5.6
There were problems such as not being able to fully utilize the conversion capability of the converter.
［問題点を解決するための手段］
この発明は、」−記問題点を解決したものであり、映像
信号を輝度信号と色信号に分解し、各信号をＡＤ変換し
たのち時分割多重する輝度・色時分割多重回路と、この
輝度・色時分割多重回路に接続され、画像メモリにて遅
延させた出力を入力に巡回的に加算することにより雑音
を低減する巡回型雑音低減回路と、この巡回型雑音低減
回路に接続され、入力を輝度信号と色信ｉｊｌに分解し
、それぞわＤＡ変換したのち混合する輝度・色信号重畳
回路とを設けて構成１．たことを特徴とするものである
。[Means for Solving the Problems] The present invention solves the problems described in ``-'', and is a method for dividing a video signal into a luminance signal and a color signal, AD converting each signal, and then time-division multiplexing the luminance signals.・A color time division multiplex circuit, a cyclic noise reduction circuit connected to the luminance/color time division multiplex circuit, and which reduces noise by cyclically adding the output delayed in the image memory to the input; 1. A luminance/chrominance signal superimposition circuit is connected to the cyclic noise reduction circuit and decomposes the input into a luminance signal and a chrominance signal, performs DA conversion on each, and then mixes the signals. It is characterized by:
［作用］
この発明は、映像信号を輝度信号と色信号に分解し、各
信号をＡＤ変換したのち時分割多重し、輝度信号と色信
号の時分割多重出力を、画像メモリを用いる弔−の巡回
型雑音低減回路に供給して雑音低減処理を施すことに、
Ｌす、巡回型雑音低減の機能を輝度信号と色信号に共通
の１回路に集約し、回路構成の簡約化を図る。[Function] The present invention decomposes a video signal into a luminance signal and a color signal, performs AD conversion on each signal, and then time-division multiplexes the output, and outputs the time-division multiplexed output of the luminance signal and color signal by using an image memory. By supplying it to a cyclic noise reduction circuit and performing noise reduction processing,
L. The cyclic noise reduction function is integrated into one circuit common to the luminance signal and color signal, thereby simplifying the circuit configuration.
［実施例］
以下、この発明の実施例について、第１図ないし第３図
を参照して説明する。第１図は、この発明の巡回型雑音
低減装置の一実施例を示す回路構成図、第２図は、第１
図に示したクロック発生回路の一実施例を示す回路図、
第３図は、第１図に示した回路各部の信号波形図である
。[Example] Hereinafter, an example of the present invention will be described with reference to FIGS. 1 to 3. FIG. 1 is a circuit configuration diagram showing an embodiment of the cyclic noise reduction device of the present invention, and FIG.
A circuit diagram showing an embodiment of the clock generation circuit shown in the figure,
FIG. 3 is a signal waveform diagram of each part of the circuit shown in FIG. 1.
第１図中、巡回型雑音低減装置２１は、映像信号を輝度
信号Ｙと色信号Ｃに分解し、各信号をＡＤ変換したのち
時分割多重する輝度・色時分割多重回路２２と、この輝
度・色時分割多重回路２２に接続され、画像メモリ２３
ａにより遅延させた出力を入力に巡回的に加算して雑音
を低減する巡回型雑音低減回路２３と、この巡回型雑音
低減回路２３に接続され、入力を輝度信号Ｙと色信号Ｃ
に分解し、それぞれＤＡ変換したのち混合する輝度・色
信号重畳回路２４及び上記回路各部にクロック信号を供
給するクロック発生回路２５からなる。In FIG. 1, a cyclic noise reduction device 21 includes a luminance/color time division multiplexing circuit 22 that decomposes a video signal into a luminance signal Y and a color signal C, performs AD conversion on each signal, and then time division multiplexes the signals. - Connected to the color time division multiplexing circuit 22 and image memory 23
A cyclic noise reduction circuit 23 that cyclically adds the output delayed by a to the input to reduce noise;
It consists of a luminance/chrominance signal superimposing circuit 24 that separates the signals into 1 and 24, performs DA conversion, and then mixes them, and a clock generation circuit 25 that supplies clock signals to each part of the circuit.
輝度・色時分割多重回路２２は、入力映像信号を輝度信
号Ｙと色信号Ｃに分解する輝度・色分離回路２に、輝度
信号用と色信号用のＡＤ変換回路２２ａ、２２ｂを接続
し、ＡＤ変換回路２’２ａは直接に、またＡＤ変換回路
２２ｂはデコード回路２２ｃを介して切り替えスイッチ
２２ｄに接続したものであり、切り替えスイッチ２２ｄ
により交互に選択した信号を巡回型雑音低減回路２３に
供給する。デコード回路２２ｃは、ディジタル信号に変
換された直角２相変調色信号Ｃを、色差信号Ｒ−Ｙ、ｌ
３−Ｙに分解するための回路であり、色信号Ｃを異なる
タイミングでラッチする２組のラッチ回路２６．２７と
２８．２９を、最終段・の切り替えスイッチ３０の切り
替え入力端子に接続したものである。一方の組のラッチ
回路２６と２７は、それぞれ後述のクロック信号Ｓｆと
ｓｈに従ってラッチ動作を行う。また、他方の組のラッ
チ回路２８．２９は、上記クロック信号Ｓｆ、Ｓｈを位
相角９０度だけ進相させて得られるクロック信号Ｓｇと
Ｓｉに従ってそれぞれラッチ動作を行う。The luminance/color time division multiplexing circuit 22 connects AD conversion circuits 22a and 22b for luminance signals and chrominance signals to a luminance/color separation circuit 2 that decomposes an input video signal into a luminance signal Y and a chrominance signal C. The AD conversion circuit 2'2a is directly connected to the changeover switch 22d, and the AD conversion circuit 22b is connected to the changeover switch 22d via the decoding circuit 22c.
The signals alternately selected are supplied to the cyclic noise reduction circuit 23. The decoding circuit 22c converts the quadrature two-phase modulated color signal C into a digital signal into color difference signals RY, l.
This is a circuit for decomposing into 3-Y, and two sets of latch circuits 26, 27 and 28, 29 that latch the color signal C at different timings are connected to the switching input terminal of the final stage switching switch 30. It is. One set of latch circuits 26 and 27 performs a latch operation according to clock signals Sf and sh, which will be described later, respectively. The latch circuits 28 and 29 of the other set perform latching operations in accordance with clock signals Sg and Si obtained by advancing the clock signals Sf and Sh by a phase angle of 90 degrees, respectively.
巡回型雑音低減回路２３は、ゲインが１．Ｋ（ただし、
０＜Ｋ＜１）である入力アブテネータ回路２３ｂを、加
算回路２３ｃを介してフィールドメモリタイプの画像メ
モリ２３ａに接続するとともに、画像メモリ２３ａの出
力をゲインがＫの帰還アッテネータ回路２３ｄを介して
加算回路２３ｃに供給する構成であり、加算回路２３ｃ
の出力が出力映像信号となる。この巡回型雑音低回路２
３は、正帰還のゲインＫを１に近づけ、相関をとる対象
となるフィールド数を増やすほど、高いＳＮ改善度が得
られる。なお、この実施例では、画像メモリ２３ａのク
ロック信号Ｓａの周波数ｆｃＫを、水平同期周波数ｆ
Ｈの８４０倍に設定しである。The cyclic noise reduction circuit 23 has a gain of 1. K (However,
0<K<1) is connected to a field memory type image memory 23a via an adder circuit 23c, and the output of the image memory 23a is added via a feedback attenuator circuit 23d with a gain of K. It is configured to supply the signal to the circuit 23c, and the adder circuit 23c
The output becomes the output video signal. This cyclic noise low circuit 2
In No. 3, as the positive feedback gain K approaches 1 and the number of fields targeted for correlation increases, a higher degree of SN improvement can be obtained. In this embodiment, the frequency fcK of the clock signal Sa of the image memory 23a is set to the horizontal synchronization frequency f.
It is set to 840 times H.
輝度・色信号重畳回路２４は、巡回型雑音低減回路２３
に接続した切り替えスイッチ２４ａの一方の切り替え出
力端子に輝度信号用のラッチ回路２４ｂを接続し、他方
の切り替え出力端子に色差信号用として一対のラッチ回
路２４．ｃ、２４ｄが接続しである。ラッチ回路２４２
Ｌは、ＤＡ変換回路２４ｅを介して輝度・色混合回路１
４に接続されている。ラッチ回路２４ｃと２４ｄは、そ
れぞれ２個のラッチ回路２４ｆ、２４ｇ及び２４ｈ。The luminance/chrominance signal superimposition circuit 24 is a cyclic noise reduction circuit 23
A latch circuit 24b for luminance signals is connected to one switching output terminal of the changeover switch 24a connected to the switch 24., and a pair of latch circuits 24b for color difference signals is connected to the other switching output terminal. c and 24d are connected. Latch circuit 242
L is connected to the luminance/color mixing circuit 1 via the DA conversion circuit 24e.
Connected to 4. The latch circuits 24c and 24d are two latch circuits 24f, 24g and 24h, respectively.
２４ｉを介してエンコード回路２４ｊに接続されており
、エンコード回路２４ｊの出力はＤＡ変換回路２４ｋを
介して輝度・色混合回路１４に供給される。24i, and the output of the encoding circuit 24j is supplied to the luminance/color mixing circuit 14 via the DA conversion circuit 24k.
クロック発生回路２５は、第２図に示したように、輝度
・色分離回路２に供給される映像信号から水平同期信号
を分離する同期分離回路３１とカ＝７−
ラーバースト信号を分離するパーストゲート回路３２を
有しており、水平同期信号に位相ロックされたクロック
信号Ｓａ（周波数ｆｃＫ）、或はカラーバースト信号に
位相ロックされたクロック信号Ｓｅ（周波数４ｆｓｃ）
を使って各種クロック信号を形成する。同期分離回路３
１には、位相比較回路３３．低域か波回路３４．電圧制
御発振器３５、Ｉ／８４０分周回路３６が、位相ロック
ドループを形成して接続してあり、電圧制御発振器３５
の出力は、ＡＤ変換回路２２ａとＤＡ変換回路２４ｅ及
び画像メモリ２３ａ用の周波数ｆｃＫ（−８４０ｆｕ）
のクロック信号Ｓａとなる。クロック信号Ｓａは、ｌ／
２分周回路３７にて分周されてクロック信号ｓｂとなり
、切り替えスイッチ２２ｄとラッチ回路２４ｂに供給さ
れる。また、１／２分周回路３７に続く１７２分周回路
３８からは、周波数が１ ／ ４ ｆ ＣＫのクロック
信号Ｓｃが後述の位相補正回路４６に供給される。さら
に、１／２分周回路３８に続く１／２分周回路３９から
は、周波数が１／８ｆｃＫのクロック信号Ｓｄが、切り
替えスイッチ３０にとラッチ回路２４ｃ。As shown in FIG. 2, the clock generation circuit 25 includes a synchronization separation circuit 31 that separates a horizontal synchronization signal from the video signal supplied to the luminance/color separation circuit 2, and a burst signal that separates a color burst signal. It has a gate circuit 32 and outputs a clock signal Sa (frequency fcK) phase-locked to the horizontal synchronization signal or a clock signal Se (frequency 4fsc) phase-locked to the color burst signal.
to form various clock signals. Synchronous separation circuit 3
1 includes a phase comparison circuit 33. Low frequency wave circuit 34. A voltage controlled oscillator 35 and an I/840 frequency divider circuit 36 are connected to form a phase locked loop.
The output is the frequency fcK (-840fu) for the AD conversion circuit 22a, the DA conversion circuit 24e, and the image memory 23a.
becomes the clock signal Sa. The clock signal Sa is l/
The clock signal sb is frequency-divided by the frequency divider circuit 37, and is supplied to the changeover switch 22d and the latch circuit 24b. Further, a clock signal Sc having a frequency of 1/4 f CK is supplied from a 172 frequency divider circuit 38 following the 1/2 frequency divider circuit 37 to a phase correction circuit 46 to be described later. Furthermore, a clock signal Sd having a frequency of 1/8fcK is sent from the 1/2 frequency divider 39 following the 1/2 frequency divider 38 to the changeover switch 30 and the latch circuit 24c.
２４ｄに供給される。ただし、ラッチ回路２４ｄは、ラ
ッチ回路２４ｃとは逆位相のクロック信号Ｓｄでもって
動作するため、インバータ回路（図示せず）等によりク
ロック信号Ｓｄを位相反転した信号がラッチ回路２４ｄ
に供給される。24d. However, since the latch circuit 24d operates with a clock signal Sd having an opposite phase to that of the latch circuit 24c, a signal obtained by inverting the phase of the clock signal Sd by an inverter circuit (not shown) or the like is sent to the latch circuit 24d.
supplied to
一方、パーストゲート回路３２には、位相比較回路４０
．サンプル・ホールド回路４１．低域が波回路４２．電
圧制御発振器４３．１／４分周回路４４が位相ロックド
ループを形成して接続しである。パーストゲート回路３
２は、パーストゲートパルス発生回路４５から供給され
るパーストゲートパルスに同期して動作し、入力映像信
号中のカラーバースト信号を抽出する。また、サンプル
・ボールド回路４１は、パーストゲートパルス発生回路
４５の出力をザンブリングクロックとし、位相比較回路
４０の出力をサンプル・ボールドする。On the other hand, the burst gate circuit 32 includes a phase comparator circuit 40.
．． Sample and hold circuit 41. Low frequency wave circuit 42. A voltage controlled oscillator 43 and a 1/4 frequency divider circuit 44 are connected to form a phase locked loop. Burst gate circuit 3
2 operates in synchronization with the burst gate pulse supplied from the burst gate pulse generation circuit 45, and extracts a color burst signal from the input video signal. Further, the sample/bold circuit 41 uses the output of the burst gate pulse generation circuit 45 as a zumbling clock, and samples/bold the output of the phase comparison circuit 40.
電圧制御発振器４３の出力は、周波数４ｆｓｃのクロッ
ク信号Ｓｅとして、ＡＤ変換回路２２ｂとＤＡ変換回路
２４ｋに供給される。また、ｌ／４分周回路４４の出力
は、周波数がｆｓｃのクロック信号Ｓｆとして、ラッチ
回路２６とラッチ回路２４ｇ、２４ ｉに供給される。The output of the voltage controlled oscillator 43 is supplied to the AD conversion circuit 22b and the DA conversion circuit 24k as a clock signal Se having a frequency of 4 fsc. Further, the output of the 1/4 frequency divider circuit 44 is supplied to the latch circuit 26 and the latch circuits 24g and 24i as a clock signal Sf having a frequency of fsc.
さらに、１／４分周回路４４からは、周波数はクロック
信号Ｓｆと同じで、位相がクロック信号Ｓｆよりも９０
度進んだクロック信号Ｓｇが、ラッチ回路２８に供給さ
れる。Furthermore, from the 1/4 frequency divider circuit 44, the frequency is the same as that of the clock signal Sf, and the phase is 90 degrees lower than that of the clock signal Sf.
The advanced clock signal Sg is supplied to the latch circuit 28.
なお、１／４分周回路４４には、クロック信号Ｓｆをク
ロック信号Ｓｃによって位相補正する位相補正回路４６
が接続してあり、この位相補正回路４６から得られる周
波数ｆ”ｓのクロック信号ｓｈが、ラッチ回路２７と’
２４ｆに供給され、クロック信号ｓｈよりも９０度位相
の進んだクロック信号Ｓｉが、ラッチ回路２９に供給さ
れる。Note that the 1/4 frequency divider circuit 44 includes a phase correction circuit 46 that corrects the phase of the clock signal Sf using the clock signal Sc.
is connected to the latch circuit 27, and the clock signal sh of frequency f''s obtained from this phase correction circuit 46 is connected to the latch circuit 27 and '
A clock signal Si, which is supplied to the latch circuit 24f and whose phase is 90 degrees ahead of the clock signal sh, is supplied to the latch circuit 29.
ところで、′−１−記構成になる巡回型雑音低減装置２
１の回路各部の信号波形は、第３図に示す通りである。By the way, the cyclic noise reduction device 2 having the configuration as described in '-1-
The signal waveforms of each part of the circuit No. 1 are as shown in FIG.
同図からも判る。にうに、輝度・色時分割多重回路２２
の出力は、切り替えスイッチ２２ｄの切り替え周期に応
じて、輝度信号Ｙの前後に色差信号Ｒ−Ｙ；’Ｂ−Ｙが
それぞれ２回ずつ交互に連なるものとなるが、画像メモ
リ回路２３ａの記憶容量節約のため、連続する２回のう
ち１回だけを画像メモリ回路２３ａに記憶するようにし
ても、各信号は、それぞれ占有帯域の２倍を越える周波
数のクロック信号にて処理されているため、原情報の欠
落を案することなく、共通の巡回型雑音低減回路２３に
よる雑音低減処理に供することかできる。すなわち、切
り替えスイッチ２２ｄの出力のうち、輝度信号Ｙに対す
る各色差信号Ｒ−Ｙ 。This can be seen from the same figure. Niuni, luminance/color time division multiplexing circuit 22
The output is the color difference signals R-Y;'B-Y that are alternately repeated twice before and after the luminance signal Y depending on the switching cycle of the changeover switch 22d, but depending on the storage capacity of the image memory circuit 23a. Even if only one out of two consecutive signals is stored in the image memory circuit 23a for economy, each signal is processed using a clock signal with a frequency more than twice the occupied band. It is possible to use the common cyclic noise reduction circuit 23 for noise reduction processing without worrying about missing original information. That is, among the outputs of the changeover switch 22d, each color difference signal RY with respect to the luminance signal Y.
Ｂ−Ｙの信号密度比は、４対１となるわけであるが、輝
度信号Ｙと色差信号Ｒ−Ｙ、 Ｂ−＝ｙのそもそもの占
有帯域を考えれば、この信号密度比のために一方の信号
だけに片寄って原情報が失われるといった不都合は生じ
ない。The signal density ratio of B-Y is 4:1, but if we consider the originally occupied bands of the luminance signal Y and the color difference signal R-Y, B-=y, one side is larger due to this signal density ratio. The inconvenience of losing the original information due to biased signals will not occur.
ごのように、」１記巡回型雑音低減装置２１は、映像信
号を輝度信号Ｙと色信号Ｃに分解してそれぞれＡＤ変換
し、色信号Ｃをデコード回路２．２ ｃにて色差信号Ｒ
−ＹとＢ−Ｙにデコードして輝度信号Ｙに時分割多重し
、得られた時分割多重出力を、画像メモリ２３ａを用い
る巡回型雑音低減口ＩＩ−
路２３に供給して雑音低減処理を施す構成であるから、
高価な画像メモリ２３ａを必要とする巡回型雑音低減回
路′２３は、１回路あればよく、これによる製造コスト
の切り下げ効果は大であり、また輝度信号Ｙと色信号Ｃ
の占有帯域を考慮して時分割比を適宜比に設定すること
により、両信号とも原情報を失うことなく時分割多重す
ることができるので、弔−の巡回型雑音低減回路２３に
て雑音低減処理を施すという回路構成の簡約化による悪
影響を懸念せずに、雑音低減の実を挙げることができる
。さらに、巡回型雑音低減回路２３の出力は、ラッチ回
路２４ ｂ、２／ｌｃ’、２／ｌｄにて輝度信号Ｙと色
差部＋−ＨＲ−Ｙ、ｒｒ−ｙに分解し、色差信号Ｒ−Ｙ
、Ｂ−Ｙをエンコード回路２４ｊにて色信号Ｃにエンコ
ードしたのち、それぞれＤＡ変換して混合する構成とし
たから、輝度信号Ｙも色信号ＣもベースバンドによるＡ
Ｄ−ＤＡ変換処理を受け、従ってヒデオテープレコーダ
の再生出力のよう１こ、輝度信吋七色信シ（の時間軸が
多少ずれているような信号であっても、ジッタの影響を
排除することができる。さらにまた、ＡＤ変換回路もＤ
Ａ変換回路も、それぞれ輝度信号に２２ａと２．４ ｅ
の２回路が、色信号用に２２ｂと２４にの２回路があれ
ばよいので、装置全体の構成を良好に簡単化することが
できる。As shown in 1., the cyclic noise reduction device 21 decomposes the video signal into a luminance signal Y and a color signal C, performs AD conversion on each, and converts the color signal C into a color difference signal R in a decoding circuit 2.2c.
-Y and B-Y are decoded and time-division multiplexed into the luminance signal Y, and the obtained time-division multiplexed output is supplied to the cyclic noise reduction port II-23 using the image memory 23a to perform noise reduction processing. Because it is configured to perform
The cyclic noise reduction circuit '23, which requires an expensive image memory 23a, only requires one circuit, which has a significant effect of reducing manufacturing costs.
By setting the time-division ratio appropriately in consideration of the occupied band, both signals can be time-division multiplexed without losing the original information. Noise reduction can be achieved without worrying about the negative effects of simplifying the circuit configuration for processing. Further, the output of the cyclic noise reduction circuit 23 is decomposed into a luminance signal Y and a color difference part +-HR-Y, rr-y by latch circuits 24b, 2/lc', and 2/ld, and a color difference signal R- Y
, B-Y are encoded into the color signal C by the encoding circuit 24j, and then each is DA-converted and mixed. Therefore, both the luminance signal Y and the color signal C are converted into A by the baseband.
To eliminate the effects of jitter even if the signal has been subjected to D-DA conversion processing and the time axes of the luminance signal and seven-color signal are slightly shifted, such as the playback output of a video tape recorder. Furthermore, the AD conversion circuit can also be
The A conversion circuit also outputs 22a and 2.4e for the luminance signal, respectively.
Since only two circuits 22b and 24 for color signals are required, the configuration of the entire device can be simplified.
なお、上記実施例において、クロック発生回路２５が発
生する各種クロック信号の周波数は、実施例に示した周
波数に限定されないのは、勿論であり、使用するΔＤ変
換回路２２ａや２２ｂ或はＤＡ変換回路２４ｅ、２４に
等の変換能力或は雑音低減対象と・なる輝度信号と色信
号の占有帯域等を考慮して、それぞれ適宜の周波数に設
定するとよい。In the above embodiments, the frequencies of the various clock signals generated by the clock generation circuit 25 are of course not limited to the frequencies shown in the embodiments, and may vary depending on the ΔD conversion circuits 22a and 22b or the DA conversion circuit used. 24e, 24, etc. or the occupied bands of the luminance signal and chrominance signal to be subjected to noise reduction, etc., it is preferable to set appropriate frequencies for each.
［発明の効果１
以上説明したように、この発明は、映像信号を輝度信号
と色信号に分解し、各信号をＡＤ変換したのち時分割多
重し、輝度信号と色信号の時分割多重出力を、画像メモ
リを用いる巡回型雑音低減回路に供給して雑音低減処理
を施し、さらに巡回型雑音低減回路の・出力を輝度信号
と色信号に分解し、それぞれＤＡ変換したのち混合する
構成としたから、巡回型雑音低減回路は１回路あればよ
く、輝度信号と色部りの占有帯域を考慮して時分割比を
設定することにより、両信号とも原情報を失うことなく
時分割多重することができるので、単一の巡回型雑音低
減回路にて雑音低減処理を施すという回路構成の簡約化
による悪影響を懸念せずに、雑音低減の実を挙げること
ができ、しかも輝度信号も色信号もベースバンドによる
ＡＤ−ＤＡ変換処理を受けるため、ビデオテープレコー
ダの再生出力のように、輝度信号と色信号の時間軸が多
少ずれているような信号であっても、ジッタの影響を排
除することができ、さらに、ＡＤ変換回路とＤＡ変換回
路も、それぞれ輝度信号と色信号用に２回路あればよい
ので、装置全体の構成を良好に簡単化できる等の優れた
効果を奏する。[Effect of the invention 1] As explained above, the present invention decomposes a video signal into a luminance signal and a chrominance signal, performs AD conversion on each signal, and then time-division multiplexes the luminance signal and chrominance signal. This is because the image memory is supplied to a cyclic noise reduction circuit that performs noise reduction processing, and the output of the cyclic noise reduction circuit is further decomposed into a luminance signal and a color signal, each of which is DA-converted and then mixed. , only one cyclic noise reduction circuit is required, and by setting the time division ratio in consideration of the occupied bands of the luminance signal and color part, both signals can be time division multiplexed without losing the original information. As a result, noise reduction can be achieved without worrying about the negative effects of simplifying the circuit configuration by performing noise reduction processing using a single cyclic noise reduction circuit. Because it undergoes AD-DA conversion processing by band, it is possible to eliminate the effects of jitter even in signals where the time axes of the luminance signal and chrominance signal are slightly shifted, such as the playback output of a video tape recorder. Furthermore, since only two AD conversion circuits and two DA conversion circuits are required for the luminance signal and the color signal, respectively, excellent effects such as the ability to simplify the configuration of the entire device can be achieved.
第１図は、この発明の巡回型雑音低減装置の一実施例を
示す回路構成図、第２図は、第１図に示したクロック発
生回路の一実施例を示す回路図、第３図は、第１図に示
した回路各部の信号波形図、第４図は、従来の巡回型雑
音低減装置の一例を示す回路構成図である。
２１、、、巡回型雑音低減装置、２２ 、 輝度・色時
分割多重回路、２３．．．巡回型雑音低減回路、２４．
’、、輝度・色信号重畳回路。FIG. 1 is a circuit diagram showing an embodiment of the cyclic noise reduction device of the present invention, FIG. 2 is a circuit diagram showing an embodiment of the clock generation circuit shown in FIG. 1, and FIG. , a signal waveform diagram of each part of the circuit shown in FIG. 1, and FIG. 4 is a circuit configuration diagram showing an example of a conventional cyclic noise reduction device. 21. Cyclic noise reduction device, 22. Luminance/color time division multiplexing circuit, 23. ．． ．． Cyclic noise reduction circuit, 24.
',, Luminance/color signal superimposition circuit.
Claims (1)
換したのち時分割多重する輝度・色時分割多重回路と、
この輝度・色時分割多重回路に接続され、画像メモリに
て遅延させた出力を入力に巡回的に加算することにより
雑音を低減する巡回型雑音低減回路と、この巡回型雑音
低減回路に接続され、入力を輝度信号と色信号に分解し
、それぞれＤＡ変換したのち混合する輝度・色信号重畳
回路とからなる巡回型雑音低減装置。a luminance/color time-division multiplexing circuit that decomposes a video signal into a luminance signal and a chrominance signal, performs AD conversion on each signal, and then time-division multiplexes the signals;
A cyclic noise reduction circuit is connected to this luminance/color time division multiplexing circuit and reduces noise by cyclically adding the output delayed in the image memory to the input; , a cyclic noise reduction device comprising a luminance/chrominance signal superimposition circuit that separates an input into a luminance signal and a chrominance signal, performs DA conversion on each, and then mixes the signals.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61153033A JPH0640673B2 (en) | 1986-06-30 | 1986-06-30 | Recursive noise reduction device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61153033A JPH0640673B2 (en) | 1986-06-30 | 1986-06-30 | Recursive noise reduction device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS639297A true JPS639297A (en) | 1988-01-14 |
| JPH0640673B2 JPH0640673B2 (en) | 1994-05-25 |
Family
ID=15553499
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61153033A Expired - Lifetime JPH0640673B2 (en) | 1986-06-30 | 1986-06-30 | Recursive noise reduction device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0640673B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05103344A (en) * | 1991-10-09 | 1993-04-23 | Victor Co Of Japan Ltd | Color noise reducer |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59122195A (en) * | 1982-12-28 | 1984-07-14 | Victor Co Of Japan Ltd | Noise reduction device of color video signal |
-
1986
- 1986-06-30 JP JP61153033A patent/JPH0640673B2/en not_active Expired - Lifetime
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59122195A (en) * | 1982-12-28 | 1984-07-14 | Victor Co Of Japan Ltd | Noise reduction device of color video signal |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05103344A (en) * | 1991-10-09 | 1993-04-23 | Victor Co Of Japan Ltd | Color noise reducer |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0640673B2 (en) | 1994-05-25 |
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