JPS6390882U - - Google Patents
Info
- Publication number
- JPS6390882U JPS6390882U JP18652086U JP18652086U JPS6390882U JP S6390882 U JPS6390882 U JP S6390882U JP 18652086 U JP18652086 U JP 18652086U JP 18652086 U JP18652086 U JP 18652086U JP S6390882 U JPS6390882 U JP S6390882U
- Authority
- JP
- Japan
- Prior art keywords
- chip
- shaped
- integrated circuit
- hybrid integrated
- component
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 claims description 2
- 239000000758 substrate Substances 0.000 claims 3
- 229910000679 solder Inorganic materials 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Details Of Resistors (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Combinations Of Printed Boards (AREA)
Description
第１図、第２図はそれぞれ本考案実施例、およ
び従来における混成集積回路の組立構造図である
。
各図において、１：上段の基板、２：下段の基
板、３：回路部品、３０：チツプ形コンデンサ、
チツプ形抵抗体等のチツプ形部品、３１：チツプ
形部品の電極部。
FIGS. 1 and 2 are diagrams showing the assembly structure of an embodiment of the present invention and a conventional hybrid integrated circuit, respectively. In each figure, 1: upper board, 2: lower board, 3: circuit components, 30: chip capacitor,
Chip-shaped parts such as chip-shaped resistors, 31: Electrode part of chip-shaped parts.
Claims (1)
板を上下段に並べ、その基板の間で対応する端子
間を相互接続して成る混成集積回路において、上
下段の基板の間に介装したチツプ形部品を基板で
直接挾持し、かつ該部品の電極部を接続リード部
材としてその上下面とこれに当接し合う上下段の
基板面との間を半田付け接合したことを特徴とす
る混成集積回路の組立構造。 (2) 実用新案登録請求の範囲第１項記載の組立
構造において、チツプ形部品がチツプ形コンデン
サないしチツプ形抵抗体等の外付け受動素子であ
ることを特徴とする混成集積回路の組立構造。[Scope of Claim for Utility Model Registration] (1) In a hybrid integrated circuit in which boards on which circuit components including chip-shaped parts are mounted are arranged in upper and lower rows, and corresponding terminals are interconnected between the boards, A chip-shaped component inserted between the two substrates is directly sandwiched between the two substrates, and the upper and lower surfaces of the component are used as connection lead members to solder and join the top and bottom surfaces of the chip-shaped component that are in contact with the upper and lower substrate surfaces. An assembly structure of a hybrid integrated circuit characterized by the following. (2) Utility model registration The assembled structure of a hybrid integrated circuit according to claim 1, wherein the chip-shaped component is an external passive element such as a chip-shaped capacitor or a chip-shaped resistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18652086U JPS6390882U (en) | 1986-12-03 | 1986-12-03 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18652086U JPS6390882U (en) | 1986-12-03 | 1986-12-03 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6390882U true JPS6390882U (en) | 1988-06-13 |
Family
ID=31136148
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18652086U Pending JPS6390882U (en) | 1986-12-03 | 1986-12-03 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6390882U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2020174941A1 (en) * | 2019-02-28 | 2020-09-03 | ソニー株式会社 | Electronic device and substrate |
-
1986
- 1986-12-03 JP JP18652086U patent/JPS6390882U/ja active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2020174941A1 (en) * | 2019-02-28 | 2020-09-03 | ソニー株式会社 | Electronic device and substrate |
| JPWO2020174941A1 (en) * | 2019-02-28 | 2021-12-23 | ソニーグループ株式会社 | Electronic equipment and boards |
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