JPS6387740A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS6387740A JPS6387740A JP23362686A JP23362686A JPS6387740A JP S6387740 A JPS6387740 A JP S6387740A JP 23362686 A JP23362686 A JP 23362686A JP 23362686 A JP23362686 A JP 23362686A JP S6387740 A JPS6387740 A JP S6387740A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- type
- conductivity type
- epitaxial layer
- concentration layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 11
- 239000012212 insulator Substances 0.000 claims description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 10
- 229910052710 silicon Inorganic materials 0.000 abstract description 10
- 239000010703 silicon Substances 0.000 abstract description 10
- 238000002955 isolation Methods 0.000 abstract description 6
- 230000007547 defect Effects 0.000 abstract description 4
- 239000013078 crystal Substances 0.000 abstract description 3
- 238000009792 diffusion process Methods 0.000 abstract description 2
- 230000001590 oxidative effect Effects 0.000 abstract 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 9
- 229910052814 silicon oxide Inorganic materials 0.000 description 9
- 238000004519 manufacturing process Methods 0.000 description 7
- 230000015572 biosynthetic process Effects 0.000 description 4
- 238000005468 ion implantation Methods 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 238000009413 insulation Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Landscapes
- Bipolar Transistors (AREA)
- Element Separation (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置に係わり、特に素子間の絶縁分離と
して絶縁物を含む溝を有する半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a groove containing an insulator as insulation separation between elements.
従来、素子間の絶縁分離は選択酸化法によって形成され
た厚い酸化膜によって行なわれていたが、この方法では
、選択酸化の際の酸化膜の素子領域への喰い込みによっ
て絶縁分離領域が広くなり半導体装置の高集積化の妨げ
になっていた。このなめシリコン基板に溝を形成し、そ
の溝内に絶縁材料や多結晶シリコンを埋設する方法が、
近年用いられるようになった。特にバイポーラ型半導体
装置では、厚いエピタキシャル層とサブコレクタ層とを
分離しなければならないので、涌分離法の採用が急務で
ある。Conventionally, insulation isolation between elements has been achieved using a thick oxide film formed by selective oxidation, but with this method, the insulation isolation area becomes wider due to the oxide film digging into the element area during selective oxidation. This has been a hindrance to higher integration of semiconductor devices. This method involves forming a groove in the silicon substrate and burying insulating material or polycrystalline silicon in the groove.
It has come into use in recent years. Particularly in bipolar semiconductor devices, since it is necessary to separate a thick epitaxial layer and a sub-collector layer, there is an urgent need to adopt the water separation method.
しかしながらバイポーラ型素子を分離する場合は、溝の
底部には高濃度のサブコレクタ層が近接する為、溝の底
部には、比較的高濃度のチャンネル・ストッパー層を形
成する必要があった。以下図面を用いて説明する。However, when bipolar elements are to be separated, a highly doped sub-collector layer is located close to the bottom of the trench, so it is necessary to form a relatively highly doped channel stopper layer at the bottom of the trench. This will be explained below using the drawings.
第４図（ａ＞（ｂ）は、従来の湧分ｇ！構造を用いた半
導体装置の製造方法を説明するための工程順に示した半
導体チップ断面図である。FIG. 4 (a>(b)) is a cross-sectional view of a semiconductor chip shown in order of steps for explaining a method of manufacturing a semiconductor device using a conventional g! structure.
まず、第４図（ａ＞に示す様にｐ型シリコン基板１上に
選択的にｎ′型ササ１３１２２層３形成し、更にｎ型エ
ピタキシャル層４を形成する６次に、全面にシリコン酸
化膜１０．シリコン窒化膜３゜を形成し、フォトレジス
ト１２をマスクにシリコン酸化膜１０．シリコン窒化膜
３０及びｐ型シリコン基板１のエツチングを行い溝１５
を設け、イオン注入法によってチャンネル・ストッパー
層７Ａを形成する。First, as shown in FIG. 4 (a), an n' type layer 13122 layer 3 is selectively formed on a p type silicon substrate 1, and an n type epitaxial layer 4 is further formed.6 Next, a silicon oxide film is formed on the entire surface. 10. A silicon nitride film 3° is formed, and using the photoresist 12 as a mask, the silicon oxide film 10. The silicon nitride film 30 and the p-type silicon substrate 1 are etched to form grooves 15.
A channel stopper layer 7A is formed by ion implantation.
次に第４図（ｂ）に示すように、満１５の表面にシリコ
ン酸化膜８を形成したのち、多結晶シリコン９を埋設し
更に多結晶シリコン表面に酸化膜１０を形成したのち、
素子形成領域にベース層５゜エミッタ層６．Ａｅ電極１
１を形成しバイポーラ型半導体装置を完成させていた。Next, as shown in FIG. 4(b), after forming a silicon oxide film 8 on the surface of the polycrystalline silicon, a polycrystalline silicon 9 is buried and an oxide film 10 is further formed on the surface of the polycrystalline silicon.
Base layer 5. emitter layer 6. in the element formation region. Ae electrode 1
1 and completed a bipolar semiconductor device.
しかしながら、上述した従来の半導体装置の構造では、
イオン注入で形成したチャンネル・ストッパー層７Ａは
、溝１５の底部だけでなく、満１５の側壁下部にも形成
され、高濃度のサブコレクタ層３とチャンネル・ストッ
パー層７Ａ間の接合容量が増加し、素子の特性が劣化し
たり１．イオン注入のダメージに起因した結晶欠陥が発
生し半導体装置の製造歩留を低下させるという欠点があ
る。However, in the structure of the conventional semiconductor device described above,
The channel stopper layer 7A formed by ion implantation is formed not only at the bottom of the groove 15 but also at the bottom of the sidewall of the trench 15, increasing the junction capacitance between the highly doped subcollector layer 3 and the channel stopper layer 7A. , the characteristics of the element may deteriorate or 1. There is a drawback that crystal defects occur due to damage caused by ion implantation, reducing the manufacturing yield of semiconductor devices.
本発明の目的は、特性の劣化が少く、製造歩留りの向上
した半導体装置を提供することにある。An object of the present invention is to provide a semiconductor device with less deterioration of characteristics and improved manufacturing yield.
本発明の半導体装置は、一導電型半導体基板上の少くと
も一部に形成された一導電型高濃度層と、一導電型高濃
度層を含む全面に形成された一導電型エビタキシャル層
と、一導電型エピタキシャル層内に形成された逆導電型
高濃度層と、逆導電型高濃度層を含む全面に形成された
逆導電型エピタキシャル層と、逆導電型エピタキシャル
層表面より前記一導電型高濃度層の内部に達し表面に絶
縁 ・膜が形成された溝と、溝中に埋込まれた多結晶シ
リコン又は絶縁物とを含んで構成される。The semiconductor device of the present invention includes a high concentration layer of one conductivity type formed on at least a portion of a semiconductor substrate of one conductivity type, and an epitaxial layer of one conductivity type formed on the entire surface including the high concentration layer of one conductivity type. , an opposite conductivity type high concentration layer formed in the one conductivity type epitaxial layer, an opposite conductivity type epitaxial layer formed on the entire surface including the opposite conductivity type high concentration layer, and the one conductivity type from the surface of the opposite conductivity type epitaxial layer. It consists of a groove that reaches inside the high concentration layer and has an insulating film formed on its surface, and polycrystalline silicon or an insulator embedded in the groove.
次に、本発明の実施例について図面を参照して説明する
。Next, embodiments of the present invention will be described with reference to the drawings.
第１図は本発明の第１の実施例の断面図である。FIG. 1 is a sectional view of a first embodiment of the invention.
第１図において、ｐ型シリコン基板１の一部には、チャ
ンネル・ストッパーを形成するｐ壁高濃度層７が形成さ
れている。そしてその上面にはｐ型エピタキシャル層２
が形成されており、このｐ型エピタキシャル層２内には
ｎ型サブコレクタ層３が形成されている。そしてこのｐ
型エピタキシャル層２上にはｎ型エピタキシャル層４が
形成されている。In FIG. 1, a p-wall high concentration layer 7 forming a channel stopper is formed in a part of a p-type silicon substrate 1. A p-type epitaxial layer 2 is formed on the upper surface of the p-type epitaxial layer 2.
is formed, and within this p-type epitaxial layer 2, an n-type sub-collector layer 3 is formed. And this p
An n-type epitaxial layer 4 is formed on the type epitaxial layer 2 .
更にｎ型エピタキシャル層４表面からｐ壁高濃度層７に
達し表面にシリコン酸化ＪＩｉ８が形成された素子分離
用の満１５が形成されており、この満１５中には多結晶
シリコン９が埋込まれている。Further, a layer 15 for element isolation is formed which reaches from the surface of the n-type epitaxial layer 4 to the p-wall high concentration layer 7 and has silicon oxide JIi 8 formed on the surface, and polycrystalline silicon 9 is embedded in this layer 15. It is rare.
尚、素子形成領域のｎ型エピタキシャル層４内にはベー
ス層５．エミツタ層６及びＡｆ電極１１からなるバイポ
ーラトランジスタが形成されている。Note that a base layer 5. A bipolar transistor consisting of an emitter layer 6 and an Af electrode 11 is formed.
このように構成された第１の実施例においては、満１５
の底部はｐ壁高濃度層７内に含まれるため、溝底部の界
面におけるチャンネルの形成を防ぐことができる。又ｐ
壁高濃度層７とｎ型サブコレクタ層３間には低濃度のｐ
型エピタキシャル層１２が介在する為に、イオン注入に
よって形成された従来構造でのチャンネル・ストッパー
層であるｐ壁高濃度層７とｎ型サブコレクタ層３との容
量増大もなく、更にｐ壁高濃度層７は、熱拡散で形成さ
れる為に、結晶欠陥の発生等の問題も生じない。In the first embodiment configured in this way, up to 15
Since the bottom of the groove is included in the p-wall high concentration layer 7, formation of a channel at the interface of the groove bottom can be prevented. Also p
A low concentration p layer is formed between the wall high concentration layer 7 and the n-type sub-collector layer 3.
Since the type epitaxial layer 12 is present, there is no increase in the capacitance of the p-wall high concentration layer 7 and the n-type sub-collector layer 3, which are channel stopper layers in the conventional structure formed by ion implantation, and the p-wall height is also reduced. Since the concentration layer 7 is formed by thermal diffusion, problems such as generation of crystal defects do not occur.
第２図は本発明の第２の実施例の断面図であり、第１図
の第１の実施例と異なる所は、ｐ壁高濃度層７がｐ型シ
リコン基板１の全面に形成されていることである。FIG. 2 is a sectional view of a second embodiment of the present invention, which differs from the first embodiment shown in FIG. It is that you are.
次に、第１図に示した第１の実施例の製造方法の一例を
第３図（ａ）〜（ｄ）を用いて説明する。Next, an example of the manufacturing method of the first embodiment shown in FIG. 1 will be explained using FIGS. 3(a) to 3(d).
まず第３図（ａ＞に示すようにｐ型シリコン基板１上に
選択的に形成したシリコン酸化膜２０をマスクにｐ壁高
濃度層７を形成する。First, as shown in FIG. 3(a), a p-wall high concentration layer 7 is formed using a silicon oxide film 20 selectively formed on a p-type silicon substrate 1 as a mask.
次に第３図（ｂ）に示すように全面に、ｐ型エピタキシ
ャル層２を成長させた後、ｎ型不純物を導入し高濃度の
ｎ型エピタキシャル層３を選択的に形成する。Next, as shown in FIG. 3(b), after growing a p-type epitaxial layer 2 over the entire surface, an n-type impurity is introduced to selectively form a highly concentrated n-type epitaxial layer 3.
次に第３図（ｃ）に示すように、全面にｎ型エピタキシ
ャル層４を成長させる。Next, as shown in FIG. 3(c), an n-type epitaxial layer 4 is grown over the entire surface.
次に第３図（ｄ）に示すように、選択的にｎ型エピタキ
シャルＭ４．ｎ型エピタキシャル層２をエツチングし、
ｐ工高濃度層７内に道連する満１５を形成する。その後
満１５の壁を酸化してシリコン酸化膜８を形成したのち
、多結晶シリコンを７ｉ４１５内に埋設後多結晶シリコ
ン表面を酸化する。Next, as shown in FIG. 3(d), the n-type epitaxial M4. Etching the n-type epitaxial layer 2,
A conductive layer 15 is formed in the p-type high concentration layer 7. Thereafter, the walls of the silicon oxide layer 8 are oxidized to form a silicon oxide film 8, and after burying polycrystalline silicon in the 7i 415, the surface of the polycrystalline silicon is oxidized.
多結晶シリコンの代りにＳ ｉ ０２等の絶縁物を埋設
してもよい。An insulator such as S i 02 may be buried instead of polycrystalline silicon.
以下通常の方法でベース層５．エミツタ層６゜Ａｆ配線
を形成する事によって第１図に示した第１の実施例が完
成する。Base layer 5. The first embodiment shown in FIG. 1 is completed by forming the emitter layer 6°Af wiring.
尚、第２図に示した第２の実施例は、第３図（ａ）にお
いて、ｐ型シリコン基板１の全面にｐ壁高濃度層７を形
成すればよく、この場合第１の実施例に比ベシリコン酸
化膜２０の形成とそのパターニング工程が不要となる利
点がある。In addition, in the second embodiment shown in FIG. 2, the p-wall high concentration layer 7 may be formed on the entire surface of the p-type silicon substrate 1 in FIG. 3(a), and in this case, the second embodiment shown in FIG. Compared to this, there is an advantage that the formation of the silicon oxide film 20 and its patterning process are unnecessary.
以上説明したように本発明は、素子分離用の清の底部に
チャンネル・ス）・ツバ−となる一導電型高濃度層が形
成され、又、この高濃度層とサブコレクタ層である逆導
電型高濃度層との間には一導電型のエピタキシャル層が
あるので、従来構造の半導体装置におけるチャンネル・
ストッパー層とサブコレクタ層との接触による容量増加
もなく、チャンネル・ストッパー形成の際の欠陥発生も
ない、従って、半導体装置の特性劣化が少なく、製造歩
留りが向上するという効果がある。As explained above, in the present invention, a high concentration layer of one conductivity type is formed at the bottom of a channel for element isolation, and this high concentration layer and a subcollector layer of an opposite conductivity type are formed. Since there is an epitaxial layer of one conductivity type between the type and the high concentration layer, the channel and
There is no increase in capacitance due to contact between the stopper layer and the sub-collector layer, and there is no occurrence of defects during formation of the channel stopper.Therefore, the characteristics of the semiconductor device are less degraded and the manufacturing yield is improved.
第１図及び第２図は本発明の第１及び第２の実施例の断
面図、第３図（ａ）〜（ｄ）は本発明の第１の実施例の
製造方法を説明する為の工程順に示した半導体チップの
断面図、第４図（ａ）（ｂ）は従来の半導体装置の製造
方法を説明するための□半導体チップの断面図である。
１・・・ｐ型シリコン基板、２・・・ｐ型エピタキシャ
ル層、３・・・ｎ型サブコレクタ層、４・・・ｎ型エピ
タキシャル層、５・・・ベース層、６・・・エミツタ層
、７・・・ｐ型窩濃度層、７Ａ・・・チャンネル・スト
ッパー層、８，１０．２０．２０Ａ・・・シリコン酸化
膜、９・・・多結晶シリコン、１１・・・ＡＦ主電極１
２・・・フオトレジス１−１３０・・・シリコン窒化膜
。1 and 2 are cross-sectional views of the first and second embodiments of the present invention, and FIGS. 3(a) to 3(d) are cross-sectional views for explaining the manufacturing method of the first embodiment of the present invention. 4(a) and 4(b) are cross-sectional views of a semiconductor chip for explaining a conventional method of manufacturing a semiconductor device. DESCRIPTION OF SYMBOLS 1...p-type silicon substrate, 2...p-type epitaxial layer, 3...n-type subcollector layer, 4...n-type epitaxial layer, 5...base layer, 6...emitter layer , 7... P-type cavity concentration layer, 7A... Channel stopper layer, 8, 10.20.20A... Silicon oxide film, 9... Polycrystalline silicon, 11... AF main electrode 1
2... Photoresist 1-130... Silicon nitride film.
Claims (1)
導電型高濃度層と、該一導電型高濃度層を含む全面に形
成された一導電型エピタキシャル層と、該一導電型エピ
タキシャル層内に形成された逆導電型高濃度層と、該逆
導電型高濃度層を含む全面に形成された逆導電型エピタ
キシャル層と、該逆導電型エピタキシャル層表面より前
記一導電型高濃度層の内部に達し表面に絶縁膜が形成さ
れた溝と、該溝中に埋込まれた多結晶シリコン又は絶縁
物とを含むことを特徴とする半導体装置。A high concentration layer of one conductivity type formed on at least a portion of a semiconductor substrate of one conductivity type, an epitaxial layer of one conductivity type formed on the entire surface including the high concentration layer of one conductivity type, and an epitaxial layer of one conductivity type formed on the entire surface including the high concentration layer of one conductivity type. an opposite conductivity type high concentration layer formed within the opposite conductivity type high concentration layer, a reverse conductivity type epitaxial layer formed on the entire surface including the opposite conductivity type high concentration layer, and one conductivity type high concentration layer formed from the surface of the opposite conductivity type epitaxial layer 1. A semiconductor device comprising: a trench that reaches inside and has an insulating film formed on its surface; and polycrystalline silicon or an insulator embedded in the trench.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61233626A JPH0715940B2 (en) | 1986-09-30 | 1986-09-30 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61233626A JPH0715940B2 (en) | 1986-09-30 | 1986-09-30 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6387740A true JPS6387740A (en) | 1988-04-19 |
| JPH0715940B2 JPH0715940B2 (en) | 1995-02-22 |
Family
ID=16957993
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61233626A Expired - Fee Related JPH0715940B2 (en) | 1986-09-30 | 1986-09-30 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0715940B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008508701A (en) * | 2004-07-28 | 2008-03-21 | クォンタム セミコンダクター リミテッド ライアビリティ カンパニー | Layout for integrated integration of CMOS and stacked photoactive layers |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59124153A (en) * | 1982-12-29 | 1984-07-18 | Matsushita Electric Ind Co Ltd | Semiconductor integrated circuit device |
| JPS60154626A (en) * | 1984-01-25 | 1985-08-14 | Hitachi Ltd | Deposition in groove and equipment thereof |
-
1986
- 1986-09-30 JP JP61233626A patent/JPH0715940B2/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59124153A (en) * | 1982-12-29 | 1984-07-18 | Matsushita Electric Ind Co Ltd | Semiconductor integrated circuit device |
| JPS60154626A (en) * | 1984-01-25 | 1985-08-14 | Hitachi Ltd | Deposition in groove and equipment thereof |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008508701A (en) * | 2004-07-28 | 2008-03-21 | クォンタム セミコンダクター リミテッド ライアビリティ カンパニー | Layout for integrated integration of CMOS and stacked photoactive layers |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0715940B2 (en) | 1995-02-22 |
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