JPS6386457A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS6386457A JPS6386457A JP61229885A JP22988586A JPS6386457A JP S6386457 A JPS6386457 A JP S6386457A JP 61229885 A JP61229885 A JP 61229885A JP 22988586 A JP22988586 A JP 22988586A JP S6386457 A JPS6386457 A JP S6386457A
- Authority
- JP
- Japan
- Prior art keywords
- bump
- bumps
- manufacturing
- semiconductor device
- gold
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 47
- 238000004519 manufacturing process Methods 0.000 title claims description 22
- 239000010931 gold Substances 0.000 claims abstract description 47
- 229910052737 gold Inorganic materials 0.000 claims abstract description 42
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims abstract description 41
- 238000000034 method Methods 0.000 claims abstract description 25
- 229910052751 metal Inorganic materials 0.000 claims abstract description 20
- 239000002184 metal Substances 0.000 claims abstract description 20
- 239000010949 copper Substances 0.000 claims abstract description 18
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 15
- 229910052802 copper Inorganic materials 0.000 claims abstract description 15
- 239000000463 material Substances 0.000 claims abstract description 6
- 238000009713 electroplating Methods 0.000 claims description 15
- 239000000758 substrate Substances 0.000 claims description 6
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 5
- 238000009792 diffusion process Methods 0.000 claims description 5
- LQBJWKCYZGMFEV-UHFFFAOYSA-N lead tin Chemical compound [Sn].[Pb] LQBJWKCYZGMFEV-UHFFFAOYSA-N 0.000 claims description 4
- 229910000679 solder Inorganic materials 0.000 claims description 4
- 229910052759 nickel Inorganic materials 0.000 claims description 3
- 230000002265 prevention Effects 0.000 claims description 3
- 229910000881 Cu alloy Inorganic materials 0.000 claims description 2
- 229910052782 aluminium Inorganic materials 0.000 claims description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 2
- 238000007747 plating Methods 0.000 abstract description 27
- 229920001721 polyimide Polymers 0.000 abstract description 4
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 239000007788 liquid Substances 0.000 abstract 1
- 230000000873 masking effect Effects 0.000 abstract 1
- 239000011521 glass Substances 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 3
- 239000004642 Polyimide Substances 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- 229910000838 Al alloy Inorganic materials 0.000 description 1
- 229910000831 Steel Inorganic materials 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 230000006355 external stress Effects 0.000 description 1
- 150000002343 gold Chemical class 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000010959 steel Substances 0.000 description 1
- 238000005406 washing Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
［発明の目的］
（産業上の利用分野）
本発明は、半導体装置の製造方法に関し、特にＴＡＢ
（Ｔａｐｅ Ａｔ１ｔ０１ａｔｅｄ Ｂｏｎｄｉｎｇ
）によりリードを半導体チップの電極部に接続する半導
体装置の製造方法に係わるものである。[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a method for manufacturing a semiconductor device, and in particular, to a method for manufacturing a semiconductor device.
(Tape At1t01ated Bonding
) relates to a method of manufacturing a semiconductor device in which leads are connected to electrode portions of a semiconductor chip.
（従来の技術）
ＩＣ，ＬＳＩ等の半導体チップは、省電力化又は利用範
囲を拡大する目的で小型化つまりポータプル化が促進さ
れてきている。また、同様にパッケージにおいても小型
化、薄型化が要求されている。更に、半導体チップでは
その上面周辺に形成された。１２電極部から外部端子へ
電極リードを取出して取扱い易くし、かつ外部応力に対
する保護を目的としてパッケージ等が施されている。(Prior Art) Semiconductor chips such as ICs and LSIs are being miniaturized, that is, made portable, for the purpose of saving power or expanding the scope of use. Similarly, packages are also required to be smaller and thinner. Furthermore, it is formed around the top surface of a semiconductor chip. The electrode leads are taken out from the 12 electrode portions to the external terminals for easy handling, and a package or the like is provided for the purpose of protection against external stress.
ところで、半導体チップのＡ℃電極から外部端子へ電極
リードを取出す方法としてはワイヤボンディング方式、
フリップチップ方式、ＴＡＢ方式等が知られている。し
かしながら、ワイヤボンディング方式は２５〜３Ｃ１ｍ
φのＡＵ、Ａｎ極細線を１本づつ順次接続する方法であ
るため、電極端子数の増大、Ａｌ２電極部のピッチ幅及
びＡｆｆｉ電極部の面積の減少等により信頼性が低下す
る問題があった。また、フリップチップ方式は、ピッチ
幅及び面積の減少と共に、接合強度の低下、更に検査が
困難であると同時に信頼性の低下も避けられないという
問題があった。これに対し、ＴＡＢ方式、特に転写原版
を使用してバンプを電極り一ドに転写し、このリードを
半導体チップの電極部に該バンプを介して接続する方法
はＡ℃電極部のピッチ幅及び面積の減少に対してもＮ極
リードの幅を変えたり、バンプの大きざを変えたりする
ことによって充分に対応でき、信頼性の高い接続が可能
とする。以下、このＴＡＢ方式による半導体装置の製造
方法を説明する。By the way, the wire bonding method is the method for taking out the electrode lead from the A℃ electrode of the semiconductor chip to the external terminal.
A flip chip method, a TAB method, etc. are known. However, the wire bonding method is 25~3C1m
Since the method involves sequentially connecting φ AU and An ultrafine wires one by one, there was a problem that reliability decreased due to an increase in the number of electrode terminals, a decrease in the pitch width of the Al2 electrode part, and a decrease in the area of the Affi electrode part. . In addition, the flip-chip method has problems such as a decrease in pitch width and area, a decrease in bonding strength, difficulty in inspection, and unavoidable decrease in reliability. On the other hand, the TAB method, especially a method in which bumps are transferred onto an electrode board using a transfer master and the leads are connected to the electrode section of a semiconductor chip via the bump, is based on the pitch width of the A℃ electrode section. The reduction in area can be sufficiently coped with by changing the width of the N-pole lead or the size of the bump, thereby enabling highly reliable connections. A method of manufacturing a semiconductor device using this TAB method will be described below.
まず、シリコンやガラスからなる基板上に導電層及び転
写性を考慮した剥離性を有する導電性層（１７０層）を
順次形成し、該ＩＴＯ層上に写真蝕刻法によりバンプの
形成予定部が開口されたマスク材としてのレジストパタ
ーンを形成して転写原版を作製する。つづいて、電気メ
ッキにより前記レジストパターンの開口部から露出した
１７０層に金からなるバンプを形成する。この際、メッ
キ金罵の均一な析出を考慮して前記原版を逆にしてメッ
キ液に浸漬し、噴上式メッキ法により電気メッキを行な
っている。ひきつづき、ポリイミド又はガラスエポキシ
系樹脂フィルムに設けられた電極リードを前記原版のバ
ンプ上に配置し、加熱したボンディングツールにより該
リードをバンプに加熱圧着する。この後、ボンディング
ツール及びリードを上昇させることによって、前記原版
のバンプが前記リードに転写される。First, on a substrate made of silicon or glass, a conductive layer and a conductive layer (170 layers) having removability in consideration of transferability are sequentially formed, and the areas where bumps are to be formed are opened on the ITO layer by photolithography. A transfer original plate is produced by forming a resist pattern as a mask material. Subsequently, bumps made of gold are formed on the 170 layers exposed through the openings of the resist pattern by electroplating. At this time, in consideration of uniform deposition of the plating gold, the original plate is turned upside down and immersed in the plating solution, and electroplating is performed by a jet plating method. Subsequently, an electrode lead provided on a polyimide or glass epoxy resin film is placed on the bump of the original plate, and the lead is heat-pressed onto the bump using a heated bonding tool. Thereafter, by raising the bonding tool and the lead, the bumps on the original plate are transferred to the lead.
次いで、半導体チップのパッシベーション膜から露出し
たＡｎ電極部（ポンディングパッド）の上方に前記リー
ドに転写されたバンプを位置させ、更に該バンプの上方
にボンディングツールを配置させる。この後、ボンディ
ングツールによりリードのバンプを前記半導体チップの
Ａｆｆｉ電極部に加熱圧着することによって、リードを
バンプを介して半導体チップのＡ２１！極部に接続し、
半導体装置を製造する。Next, the bumps transferred to the leads are positioned above the An electrode portions (ponding pads) exposed from the passivation film of the semiconductor chip, and a bonding tool is placed above the bumps. Thereafter, the bumps of the leads are heat-pressed to the Affi electrode portion of the semiconductor chip using a bonding tool, and the leads are attached to the A21! of the semiconductor chip through the bumps. Connect to the pole,
Manufacture semiconductor devices.
しかしながら、上述したＴＡＢ方式にあってはバンプが
金（Ａｕ ）により形成されているため、半導体チップ
の電極数が増大するに伴って使用するＡｔ１ｆｆｉが増
加し、コストの高騰化を招く問題があった。また、ＡＬ
Ｉのメッキ液（例えば日本エレクトロブレーティングエ
ンジニャーズ社製商品名二二ュートロネクス３０９、ニ
ュートロネクス２１０ｆｌ）は管理が難かしいため、メ
ッキ条件（温度、電流密度、ｐＨ，Ａｕ含有量、不純物
等）の少しの変化で、形成されたバンプ形状やバンプの
性質が変わるという問題があった。However, in the above-mentioned TAB method, since the bumps are formed of gold (Au), the amount of At1ffi used increases as the number of electrodes on the semiconductor chip increases, leading to a rise in cost. Ta. Also, AL
The plating solution (for example, Nitronex 309, Neutronex 210fl manufactured by Nippon Electroblating Engineers) is difficult to manage, so the plating conditions (temperature, current density, pH, Au content, impurities, etc.) There is a problem in that a slight change in the bump shape and the properties of the bump formed change.
（発明が解決しようとする問題点）
本発明は、上記従来の問題点を解決するためになされた
もので、Ａｌｌメッキ液に比べてメッキ管理がし易いメ
ッキ液によりバンプの大部分を構成する金属膜の形成が
可能で、コストの低減化を図ることができ、更に電極リ
ードを該バンプを介して半導体チップの電極部に良好に
接合し得る半導体装置の製造方法を提供しようとするも
のである。(Problems to be Solved by the Invention) The present invention has been made in order to solve the above-mentioned problems of the conventional art.Most of the bumps are formed using a plating solution that is easier to control than the All plating solution. The object of the present invention is to provide a method for manufacturing a semiconductor device in which a metal film can be formed, the cost can be reduced, and an electrode lead can be well bonded to an electrode part of a semiconductor chip via the bump. be.
［発明の構成］
（問題点を解決するための手段）
本発明は、基板上に導電層が被覆され、かつ所望の開口
部を有するマスク材が設けられた転写原版に電気メッキ
に、よりバンプを形成し、このバンプをリードに転写し
た後、このリードをバンプを介して半導体チップの所定
の電極部に接続する半導体装置の製造において、前記転
写原版の開口部に金層を形成し、該金層上に金とは異な
る金属膜を電気メッキにて形成することによりバンプを
作製せしめることを特徴とする半導体装置の製造方法で
ある。[Structure of the Invention] (Means for Solving the Problems) The present invention provides bumps by electroplating on a transfer original plate in which a conductive layer is coated on a substrate and a mask material having desired openings is provided. In manufacturing a semiconductor device in which the bumps are transferred to leads and the leads are connected to predetermined electrode portions of a semiconductor chip via the bumps, a gold layer is formed in the openings of the transfer original plate and the leads are transferred to the leads. This method of manufacturing a semiconductor device is characterized in that bumps are produced by forming a metal film different from gold on a gold layer by electroplating.
上記基板としては、例えばガラス、セラミックス、シリ
コン、又は金属等からなるものを挙げることができる。Examples of the substrate include those made of glass, ceramics, silicon, or metal.
上記導′Ｒ層は、例えば基板表面にスパッタリングや蒸
着により堆積されたＣｒ、Ｎｉ、ｌ”ｉ、Ｃｕ 、Ａａ
等の第１導電層と、Ａｌ１に対して適度の剥離性を有す
るＰｔ、ＩＴＯなどからなる第２導電層とから構成され
る。The conductive layer is made of, for example, Cr, Ni, l''i, Cu, Aa deposited on the surface of the substrate by sputtering or vapor deposition.
and a second conductive layer made of Pt, ITO, etc., which has appropriate releasability to Al1.
上記マスク材としては、例えば写真蝕刻法により形成さ
れたレジストパターン、ポリイミドパターン、該レジス
トパターンをマスクとしてパターニングされた５ｉｎ２
や５ｉｉＮ４のパターン等を挙げることができる。Examples of the above-mentioned mask material include a resist pattern formed by photolithography, a polyimide pattern, and a 5in2 pattern formed using the resist pattern as a mask.
and 5iiN4 patterns.
上記半導体チップの電極部は、通常、アルミニウム又は
アルミニウム合金により形成される。The electrode portion of the semiconductor chip is usually made of aluminum or an aluminum alloy.
上記金層の厚さは、コストを低減させる等の観点から５
μｍ以下にすることが望ましい。The thickness of the gold layer is set at 5.5 mm from the viewpoint of reducing costs.
It is desirable that the thickness be less than μm.
上記金とは異なる金属膜は、例えば銅、銅合金や錫−鉛
系はんだ、錫−鉛系はんだを主成分とする金属等を電気
メッキすることにより形成される。The metal film different from gold is formed, for example, by electroplating copper, a copper alloy, a tin-lead solder, a metal whose main component is tin-lead solder, or the like.
（作用）
しかして、本発明は転写原版側に位置する金層とこの金
層上に電気メッキにより形成された金とは異なる金属膜
とからバンプを作製するため、バンプ中に占める金の量
を大幅に低減でき、ひいては半導体装置の製造コストを
低減できる。また、金メッキに比べてメッキ管理が容易
なメッキ液によりバンプの大部分を構成する金属膜を形
成できるため、安定した性能を有するバンプを得ること
ができる。更に、バンプをフィルムリードに転写した状
態では該リードと反対側に金層が位置され、バンプと半
導体チップの電極部の接合は金層側でなされるため、該
電極部に対してバンプを良好に接続できる。(Function) According to the present invention, since bumps are made from a gold layer located on the transfer master side and a metal film different from gold formed by electroplating on this gold layer, the amount of gold occupied in the bumps is can be significantly reduced, and in turn, the manufacturing cost of semiconductor devices can be reduced. Furthermore, since the metal film that constitutes most of the bump can be formed using a plating solution that is easier to control than gold plating, it is possible to obtain bumps with stable performance. Furthermore, when the bumps are transferred to the film leads, the gold layer is located on the opposite side of the leads, and the bond between the bumps and the electrodes of the semiconductor chip is made on the gold layer side. can be connected to.
（発明の実施例）
以下、本発明の実施例を第１図（ａ）〜（ｅ）を参照し
て説明する。(Embodiments of the Invention) Hereinafter, embodiments of the present invention will be described with reference to FIGS. 1(a) to (e).
まず、ガラス基板１上に導電膜としての厚さ１０００人
のＣｒ１１２及びＩＴＯＩＩ（Ｉ ｎ５ｎｏ２）３を蒸
着法により順次形成した後、該ＩＴＯＩＩａ上に写真蝕
刻法によりバンプの形成予定部が開口されたマスク材と
してのレジストパターン４を形成して転写原版５を作製
した。First, Cr112 and ITOII (In5no2)3 having a thickness of 1000 nm as a conductive film were sequentially formed on a glass substrate 1 by vapor deposition, and then a portion where bumps were to be formed was opened on the ITOIIa by photolithography. A transfer original plate 5 was prepared by forming a resist pattern 4 as a mask material.
つづいて、前記転写原版５を電気金メッキ液（日本エレ
クトロブレーティングエンジニャーズ社製商品名二二ュ
ートロネクス３０９）中に逆にして浸漬、つまりレジス
トパターン４が下面側となるように浸漬した後、メッキ
液を噴上させて電気金メッキ処理を施してレジストパタ
ーン４から露出する１７０層３上に厚さ１μｍの金層６
を形成した。Subsequently, the transfer master plate 5 was immersed upside down in an electrolytic gold plating solution (trade name: 22 Eutronex 309, manufactured by Nippon Electroblating Engineers Co., Ltd.), that is, immersed so that the resist pattern 4 was on the lower side. A gold layer 6 with a thickness of 1 μm is formed on the 170 layer 3 exposed from the resist pattern 4 by spouting a plating solution and performing electroplating.
was formed.
ひきつづぎ、前記転写原版５を水洗した後、電気銅メッ
キ液（例えば日本エレクトロブレーティングエンジニャ
ーズ社製商品名；キューパスＭ）に前記Ａｕメッキ処理
と同様に逆さにして浸漬し、電気銅メッキ処理を施して
前記金層６及びレジストパターン４の開口部周辺の領域
上に厚さ１５μｍの銅［１７を形成した。こうした工程
により金層６と銅膜７からなるバンプ８が形成された（
第１図（ａ）図示）。Subsequently, after washing the transfer original plate 5 with water, it is immersed upside down in an electrolytic copper plating solution (for example, product name: Q-Pass M manufactured by Nippon Electroblating Engineers Co., Ltd.) in the same way as in the Au plating process, and the electrolytic copper is A copper layer [17] having a thickness of 15 μm was formed on the gold layer 6 and the region around the opening of the resist pattern 4 by plating. Through these steps, bumps 8 made of gold layer 6 and copper film 7 were formed (
FIG. 1(a) (Illustrated).
次いで、同図（ｂ）に示すようにポリイミドフィルム９
上に設けられた表面に３ｎメツキ処理が施されたＣｕ電
極リード１０を前記転写原版５のバンプ８上に配置し、
加熱したボンディングツール１１により該電極リード１
０をバンプ８に２８０℃、０．５に９の条件で２秒間加
熱圧着した。この後、ボンディングツール１１及び電極
リード１０を上昇させることによって、同図（Ｃ）に示
すように転写原版５のバンプ８を電極リード１０に転写
された。Next, as shown in the same figure (b), the polyimide film 9
A Cu electrode lead 10 whose surface has been subjected to a 3N plating process is placed on the bump 8 of the transfer original plate 5,
The electrode lead 1 is bonded by the heated bonding tool 11.
0 to the bump 8 under the conditions of 280° C. and 0.5 to 9 for 2 seconds. Thereafter, by raising the bonding tool 11 and the electrode lead 10, the bumps 8 of the transfer original plate 5 were transferred to the electrode lead 10 as shown in FIG.
次いで、同図（ｄ）に示すように半導体チップ１２のパ
ッシベーションｇ１１３から露出したＡａｆｆｉ？４部
（ポンディングパッド）１４の上方に重陽リード１０に
転写されたバンプ８を位置させ、更に該バンプ８の上方
にボンディングツール１１を配置させた。Next, as shown in FIG. 3(d), Aaffi? exposed from the passivation g113 of the semiconductor chip 12 is exposed. The bump 8 transferred to the heavy positive lead 10 was placed above the fourth part (bonding pad) 14, and the bonding tool 11 was further placed above the bump 8.
つづいて、ボンディングツール１１により電極り一ド１
０のバンプ８を半導体チップ１２のＡｆｆｉ電極部１４
に４５０℃、３ Ｋｇの条件で２秒間加熱圧着すること
によって、同図（ｅ）に示すように電極リード１０をバ
ンプ８を介して半導体チップ１２のＡ２電極部１４に接
続して半導体装置を製造した。Next, the bonding tool 11 is used to bond the electrode 1.
0 bump 8 to the Affi electrode part 14 of the semiconductor chip 12
By heat-pressing for 2 seconds at 450° C. and 3 kg, the electrode lead 10 is connected to the A2 electrode portion 14 of the semiconductor chip 12 via the bump 8, as shown in FIG. Manufactured.
得られた半導体装置は、半導体チップ１２のＡ℃電極部
１４にバンプ８の金！６を介してＡｆｆｉ−ＡＬＩ接合
となるため、従来の金バンプと同様に信頼性の高い接合
を達成できた。また、従来の金バンプを使用する場合に
比べて金の使用量が１／４以下で済んだ。更に、バンプ
８の大部分は電気銅メッキにより形成できるため、メッ
キ液温度、電流密度、ｐ）−１等のメッキ管理が容易と
なり、目的とする形状のバンプを再現性よく形成できた
。The obtained semiconductor device has gold bumps 8 on the A°C electrode portion 14 of the semiconductor chip 12! Since Affi-ALI bonding was achieved through 6, it was possible to achieve a highly reliable bond similar to that of conventional gold bumps. Furthermore, the amount of gold used is less than 1/4 compared to the case where conventional gold bumps are used. Further, since most of the bumps 8 can be formed by electrolytic copper plating, it is easy to control the plating solution temperature, current density, p)-1, etc., and it is possible to form bumps in the desired shape with good reproducibility.
なお、上記実施例においてはバンプ８を、レジストパタ
ーン４の開口部の厚さ程度の金層６と該金層６及びレジ
ストパターン４周辺にする領域上に）形成された銅ｍ（
金属ｍ１）７とにより作製したが、これに限定されず、
例えば第２図〜第４図に示す構造のバンプを作製しても
よい。In the above embodiment, the bumps 8 are made of a copper m(
Although it was made with metal m1)7, it is not limited to this,
For example, bumps having structures shown in FIGS. 2 to 4 may be manufactured.
即ち、第２図に示す構造のバンプ８は銅膜７上に更に電
気メッキにより厚さ１μｍの金層１５を形成して作製し
たものである。このようなバンプ８を用いれば、バンプ
８と電極リード（ＳｎメッキＣｕリード）との接合が前
記金層１５を介してなされるため、その接合がＡｕ−８
ｎ共晶となり、従来のＡｕバンプと全く同様に信頼性の
高い半導体装置の製造が可能となる。That is, the bump 8 having the structure shown in FIG. 2 is manufactured by further forming a gold layer 15 with a thickness of 1 μm on the copper film 7 by electroplating. If such a bump 8 is used, the bump 8 and the electrode lead (Sn-plated Cu lead) are bonded via the gold layer 15, and the bond is made of Au-8.
It becomes an n-eutectic, and it becomes possible to manufacture a highly reliable semiconductor device in exactly the same way as a conventional Au bump.
第３図に示す構造のバンプ８は、形成すべきバンプ厚さ
より若干厚いレジストパターン１６を形成した転写原版
５を用い、該レジストパターン１６の開口部の底部に露
出するＩＴＯＪｉ３上に金層６を電気メッキにより形成
した後、電気銅メッキにより同開口部内に銅１１０７を
形成することによって作製されたものである。つまり、
第３図により作製されたバンプ８は金層６と銅膜７が同
一面積となる。かかるバンプ８を用いれば、確実にバン
プ８の金層６で半導体チップのＡβ電極部に接合でき、
接合の信頼性を実施例のバンプを使用する場合に比べて
向上できる。The bump 8 having the structure shown in FIG. 3 uses a transfer original plate 5 on which a resist pattern 16 slightly thicker than the thickness of the bump to be formed is formed, and a gold layer 6 is deposited on the ITOJi 3 exposed at the bottom of the opening of the resist pattern 16. It was manufactured by electroplating and then forming copper 1107 in the opening by electroplating. In other words,
In the bump 8 manufactured as shown in FIG. 3, the gold layer 6 and the copper film 7 have the same area. If such a bump 8 is used, the gold layer 6 of the bump 8 can be reliably bonded to the Aβ electrode portion of the semiconductor chip.
The reliability of bonding can be improved compared to the case where the bumps of the embodiments are used.
第４図の示す構造のバンプ８は、形成すべきバンプ厚さ
より若干厚いレジストパターン１６を形成した転写原版
５を用い、該レジストパターン１６の開口部の底部に露
出したＩＴＯ層３上に金層６を宵気メッキにより形成し
た後、電気鋼メッキにより同開口部内に銅膜７を形成し
、更に該Ｗ４膜７上に金層１５を電気メッキにより形成
することによって作製されたものである。このような構
成によれば、前述した第２図及び第３図図示のバンプの
両方を兼ね園えたバンプを実現できる。The bump 8 having the structure shown in FIG. 4 uses a transfer original plate 5 on which a resist pattern 16 is formed which is slightly thicker than the thickness of the bump to be formed, and a gold layer is placed on the ITO layer 3 exposed at the bottom of the opening of the resist pattern 16. 6 was formed by evening plating, a copper film 7 was formed in the same opening by electric steel plating, and a gold layer 15 was further formed on the W4 film 7 by electroplating. According to such a configuration, it is possible to realize a bump that functions as both the bumps shown in FIGS. 2 and 3 described above.
また、金層と金属膜との間にニッケル層等の金と金属の
相互拡散を防止する拡散防止層を形成してバンプを作製
してもよい。Further, a bump may be produced by forming a diffusion prevention layer such as a nickel layer between the gold layer and the metal film to prevent mutual diffusion of gold and metal.
［発明の効果コ
以上詳述した如く、本発明によればＡｌｌメッキ液に比
べてメッキ管理がし易いメッキ液によりバンプの大部分
を構成する金属膜の形成が可能で、更に電極リードを該
バンプを介して半導体チップの電極部に良好に接合し得
る低コストで信頼性の高い半導体装置の製造方法を提供
できる。[Effects of the Invention] As detailed above, according to the present invention, it is possible to form the metal film constituting most of the bumps using a plating solution that is easier to control than the All plating solution, and it is also possible to form the metal film that makes up the majority of the bump. It is possible to provide a method for manufacturing a low-cost, highly reliable semiconductor device that can be well bonded to an electrode portion of a semiconductor chip via a bump.
第１図（ａ）〜（ｅ）は本発明の実施例における半導体
装置の製造工程を示す断面図、第２図〜第４図は夫々本
発明の他の実施例を示す断面図である。
１−！！板、２・Ｃｒ Ｆｆｊｒ、 ３・Ｉ ７０層、
４．１６・・・レジストパターン、５・・・転写原版、
６．１５・・・金層、７・・・銅膜、８・・・バンプ、
１０・・・電極リード、１２・・・半導体チップ、１４
・・・Ａ℃電極部。FIGS. 1A to 1E are cross-sectional views showing the manufacturing process of a semiconductor device according to an embodiment of the present invention, and FIGS. 2 to 4 are cross-sectional views showing other embodiments of the present invention, respectively. 1-! ! Plate, 2・Cr Ffjr, 3・I 70 layers,
4.16...Resist pattern, 5...Transfer original plate,
6.15... Gold layer, 7... Copper film, 8... Bump,
10... Electrode lead, 12... Semiconductor chip, 14
...A℃ electrode part.
Claims (7)
を有するマスク材が設けられた転写原版に電気メッキに
よりバンプを形成し、このバンプをリードに転写した後
、このリードをバンプを介して半導体チップの所定の電
極部に接続する半導体装置の製造において、前記転写原
版の開口部に金層を形成し、該金層上に金とは異なる金
属膜を電気メッキにて形成することによりバンプを作製
せしめることを特徴とする半導体装置の製造方法。(1) Bumps are formed by electroplating on a transfer master plate in which a conductive film is coated on a substrate and a mask material having desired openings is provided. After transferring the bumps to leads, the leads are transferred to bumps. In manufacturing a semiconductor device that is connected to a predetermined electrode portion of a semiconductor chip via a gold layer, a gold layer is formed in the opening of the transfer master, and a metal film different from gold is formed on the gold layer by electroplating. 1. A method for manufacturing a semiconductor device, comprising: manufacturing bumps.
ことを特徴とする特許請求の範囲第１項記載の半導体装
置の製造方法。(2) The method for manufacturing a semiconductor device according to claim 1, wherein the electrode portion of the semiconductor chip is made of aluminum.
合金であることを特徴とする特許請求の範囲第１項記載
の半導体装置の製造方法。(3) The method for manufacturing a semiconductor device according to claim 1, wherein the metal film formed by electroplating is copper or a copper alloy.
はんだ又は錫−鉛系はんだを主成分とする金属であるこ
とを特徴とする特許請求の範囲第１項記載の半導体装置
の製造方法。(4) Manufacturing a semiconductor device according to claim 1, wherein the metal film formed by electroplating is tin-lead solder or a metal whose main component is tin-lead solder. Method.
され該金と金属との拡散を防止する拡散防止層から作製
せしめることを特徴とする特許請求の範囲第１項記載の
半導体装置の製造方法。(5) The semiconductor according to claim 1, wherein the bump is made of a gold layer, a metal film, and a diffusion prevention layer interposed between these to prevent diffusion of the gold and metal. Method of manufacturing the device.
る特許請求の範囲第５項記載の半導体装置の製造方法。(6) The method for manufacturing a semiconductor device according to claim 5, wherein the diffusion prevention layer is made of nickel.
とする特許請求の範囲第１項記載の半導体装置の製造方
法。(7) The method for manufacturing a semiconductor device according to claim 1, further comprising forming a gold layer on the surface of the metal film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61229885A JPS6386457A (en) | 1986-09-30 | 1986-09-30 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61229885A JPS6386457A (en) | 1986-09-30 | 1986-09-30 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6386457A true JPS6386457A (en) | 1988-04-16 |
Family
ID=16899234
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61229885A Pending JPS6386457A (en) | 1986-09-30 | 1986-09-30 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6386457A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63240049A (en) * | 1987-03-27 | 1988-10-05 | Matsushita Electric Ind Co Ltd | Manufacture of bump for reprication |
-
1986
- 1986-09-30 JP JP61229885A patent/JPS6386457A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63240049A (en) * | 1987-03-27 | 1988-10-05 | Matsushita Electric Ind Co Ltd | Manufacture of bump for reprication |
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