JPS638624B2 - - Google Patents

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Publication number
JPS638624B2
JPS638624B2 JP53140285A JP14028578A JPS638624B2 JP S638624 B2 JPS638624 B2 JP S638624B2 JP 53140285 A JP53140285 A JP 53140285A JP 14028578 A JP14028578 A JP 14028578A JP S638624 B2 JPS638624 B2 JP S638624B2
Authority
JP
Japan
Prior art keywords
region
semiconductor
gate
current
gate electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP53140285A
Other languages
Japanese (ja)
Other versions
JPS5565463A (en
Inventor
Junichi Nishizawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Priority to JP14028578A priority Critical patent/JPS5565463A/en
Publication of JPS5565463A publication Critical patent/JPS5565463A/en
Publication of JPS638624B2 publication Critical patent/JPS638624B2/ja
Granted legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/7722—Field effect transistors using static field induced regions, e.g. SIT, PBT

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Junction Field-Effect Transistors (AREA)

Description

【発明の詳細な説明】 本発明は、半導体基板の一主表面にＵ字型に切
り込み領域を設け、この切り込み領域底部に絶縁
物層を形成し、この上にソース、ドレイン間を流
れる電流を制御するゲート電極を有する半導体集
積回路の新規な構造に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention provides a U-shaped cut region on one main surface of a semiconductor substrate, forms an insulating layer at the bottom of the cut region, and overlies a current flowing between a source and a drain. The present invention relates to a novel structure of a semiconductor integrated circuit having a controlling gate electrode.

半導体基板の主表面にほぼ垂直な方向に電流を
流す縦型構造は、個別デバイスとしては単位面積
当りの電流を大きくでき、しかも耐圧を大きく取
れて、走行時間の制限による上限周波数も高くて
優れている。同時に集積回路（以下ICと称す。）
としては、集積密度が高く取れるという利点を有
している。縦型構造デバイスとしてＶ字型絶縁ゲ
ート型電界効果トランジスタ（以下Ｖ―MOS
FETと称す。）があるが、ゲートの切り込み構造
がＶ字型であるため面積利用効率が悪く、電流も
それ程には大きくならず、集積度も上りにくい。 The vertical structure, which allows current to flow in a direction almost perpendicular to the main surface of the semiconductor substrate, is superior as an individual device because it allows a large current per unit area, a high withstand voltage, and a high upper limit frequency due to the limited running time. ing. At the same time, integrated circuits (hereinafter referred to as ICs)
As such, it has the advantage of high integration density. V-shaped insulated gate field effect transistor (V-MOS) is a vertical structure device.
It is called FET. ), but since the gate notch structure is V-shaped, the area utilization efficiency is poor, the current is not large enough, and the degree of integration is difficult to increase.

叙上の従来の欠点を除去した縦型構造のＵ字型
半導体装置が本願発明者から提案されている（特
公昭57―35591号）ので、まずこれについて説明
する。 The inventor of the present invention has proposed a vertically structured U-shaped semiconductor device (Japanese Patent Publication No. 57-35591) which eliminates the above-mentioned conventional drawbacks, so this will be explained first.

第１図ａ乃至ｃはＵ字型半導体装置の一実施例
の断面図である。 FIGS. 1a to 1c are cross-sectional views of one embodiment of a U-shaped semiconductor device.

第１図ａ，ｂはＵ字型絶縁ゲート静電誘導トラ
ンジスタ（以下Ｕ―MOS SITと称す。）の例で
あり、第１図ｃは同じくＵ字型接合型静電誘導ト
ランジスタ（以下Ｕ―Ｊ SITと称す。）の例で
ある。第１図ａで、n+領域１、ｐ領域２、ｎ領
域３、n+基板４はそれぞれソース領域、チヤン
ネル形成領域、ドレイン高抵抗領域、ドレイン領
域である。１′，４′，５はソース電極、ドレイン
電極、ゲート電極である。ゲート電極はAl、Mo
等の金属でもよいし、低抵抗ポリシリコンでもよ
い。６は、SiO2、Si3N4、Al2O3やその他の絶縁
層もしくはこれらの複合絶縁膜である。 Figures 1a and b are examples of a U-shaped insulated gate static induction transistor (hereinafter referred to as U-MOS SIT), and Figure 1c is an example of a U-shaped junction type static induction transistor (hereinafter referred to as U-MOS SIT). (referred to as J SIT). In FIG. 1A, an n + region 1, a p region 2, an n region 3, and an n + substrate 4 are a source region, a channel forming region, a drain high resistance region, and a drain region, respectively. 1', 4', and 5 are a source electrode, a drain electrode, and a gate electrode. Gate electrode is Al, Mo
It may be made of metal such as, or may be made of low resistance polysilicon. 6 is an insulating layer of SiO 2 , Si 3 N 4 , Al 2 O 3 or another insulating layer, or a composite insulating film of these.

第１図ｂは、ソースがn+基板１１になつてい
る、いわゆる倒立型構造SITである。１２，１
３，１４，１５，１６，１１′，１４′はそれぞれ
第１図ａの２，３，４，５，６，１′，４′に相当
する。第１図ｃは、ゲートがp+領域２４で構成
された例である。n+領域２１、n-領域２２、n+
領域２３は、それぞれソース領域、チヤンネル領
域、ドレイン領域である。２１′，２３′，２４′
はソース電極、ドレイン電極、ゲート電極であ
る。２５，２６は前述したような絶縁層である。
第１図ａ乃至ｃで、n+基板をドレインもしくは
ソースとしたが、ｐ基板中のn+埋込み領域とし
てもよいことは勿論である。第１図で、チヤンネ
ル領域は比較的低不純物密度で、しかも短チヤン
ネルに構成されている。従つて、ドレイン電圧の
影響がソース領域近傍もしくはソース領域内の一
部に及ぶことから不飽和型電流電圧特性を示す
SITとなつている。第１図はＵ字型SITの個別デ
バイスの例を示している。電流はドレインからソ
ースに流れ、ソース前面にできる電位障壁により
制御される。第１図ａ，ｂではｎ領域により、
又、第１図ｃではゲート、ドレイン間のn-領域
により耐圧が向上する。従つて電流密度が大き
く、耐圧の大きいデバイスとなる。Ｕ字型構造で
あるため、チヤンネルを緻密に配置できることが
電流密度を高くする。 FIG. 1b shows a so-called inverted structure SIT in which the source is an n + substrate 11. 12,1
3, 14, 15, 16, 11', and 14' correspond to 2, 3, 4, 5, 6, 1', and 4' in FIG. 1a, respectively. FIG. 1c shows an example in which the gate is composed of a p + region 24. n + area 21, n - area 22, n +
The regions 23 are a source region, a channel region, and a drain region, respectively. 21', 23', 24'
are the source electrode, drain electrode, and gate electrode. 25 and 26 are insulating layers as described above.
In FIGS. 1a to 1c, the n + substrate is used as the drain or source, but it goes without saying that the n + buried region in the p substrate may also be used. In FIG. 1, the channel region has a relatively low impurity density and is configured as a short channel. Therefore, since the drain voltage affects the vicinity of the source region or a part of the source region, it exhibits unsaturated current-voltage characteristics.
It has become SIT. FIG. 1 shows an example of a U-shaped SIT individual device. Current flows from the drain to the source and is controlled by a potential barrier created in front of the source. In Figures 1a and b, by the n region,
In addition, in FIG. 1c, the breakdown voltage is improved due to the n - region between the gate and drain. Therefore, the device has a high current density and a high breakdown voltage. Due to the U-shaped structure, the channels can be arranged densely, which increases the current density.

しかしながら叙上のＵ字型半導体装置を集積回
路に応用しようとした場合、多出力をとることが
難しい。 However, when trying to apply the above-mentioned U-shaped semiconductor device to an integrated circuit, it is difficult to obtain multiple outputs.

本発明は叙上の欠点を除去した縦型構造の絶縁
ゲート型Ｕ字型半導体集積回路を提供することを
目的としている。 SUMMARY OF THE INVENTION An object of the present invention is to provide a vertically structured insulated gate U-shaped semiconductor integrated circuit which eliminates the above-mentioned drawbacks.

高速低消費電力で動作するICとして、接合ゲ
ートSITを用いたI2L型インバータが周知である
が、ゲートを順方向にバイアスした時にごくわず
かな少数キヤリアの注入があり、この少数キヤリ
アの蓄積効果のために高速動作を困難にしてい
た。また、インジエクタからの電流が、インバー
タを通つて流れるため、特にフアンアウト数を大
きく（多出力に）した時に大電流を要し、消費電
力が大きくなる欠点があつた。本発明は、前述の
I2L型インバータとは異なり、全く純粋な容量結
合による効果（静電誘導効果）を用いた動作原理
に基づき少数キヤリア注入の無く、フアンアウト
数が大きいインバータを提供することにより、さ
らに高速のICを実現するものである。 I 2 L type inverters using junction gate SIT are well known as ICs that operate at high speed and low power consumption, but when the gate is forward biased, a very small number of minority carriers are injected, and this minority carrier accumulation The effect made high-speed operation difficult. Furthermore, since the current from the injector flows through the inverter, a large amount of current is required, especially when the number of fanouts is increased (multiple outputs), resulting in increased power consumption. The present invention is based on the above-mentioned
Unlike I 2 L-type inverters, we provide an inverter with a large fanout number without minority carrier injection based on the operating principle that uses a completely pure capacitive coupling effect (electrostatic induction effect), thereby achieving even higher speeds. It realizes IC.

以下図面を参照して本発明を詳細に説明する。 The present invention will be described in detail below with reference to the drawings.

第２図は本発明のＵ―MOS SITを用いた１入
力３出力のインバータである。 FIG. 2 shows a 1-input, 3-output inverter using the U-MOS SIT of the present invention.

第２図ａは等価回路、第２図ｂは平面図、第２
図ｃはAA′線に沿う断面図である。入力Vioが低
レベルにある時は、インバータ用Ｕ―MOS
SITTr2は遮断状態にあり、インジエクタTr1の
電流は前段のインバータに流れる。前段のインバ
ータが遮断状態になつて、Vioが高レベルになる
とインジエクタTr1の電流はインバータTr2のゲ
ートの電位を高くし、Tr2を導通状態に変化させ
る。Tr2のゲートが所定の電圧まで上ると、イン
ジエクタTr1の電流は、Tr3を通つて流れるよう
になる。n+領域４１，４３，４４，４５はそれ
ぞれソース領域、インジエクタTr1のドレイン領
域、ソース領域、Tr2のドレイン領域である。 Figure 2a is an equivalent circuit, Figure 2b is a plan view,
Figure c is a sectional view taken along line AA'. When input V io is at low level, U-MOS for inverter
SITTr 2 is in a cutoff state, and the current in injector Tr 1 flows to the previous stage inverter. When the inverter at the previous stage is cut off and V io becomes high level, the current in injector Tr 1 increases the potential at the gate of inverter Tr 2 , turning Tr 2 into a conductive state. When the gate of Tr 2 rises to a predetermined voltage, the current of injector Tr 1 will start flowing through Tr 3 . The n + regions 41, 43, 44, and 45 are a source region, a drain region of injector Tr 1 , a source region, and a drain region of Tr 2, respectively.

４３′はインジエクタTr1のドレイン電極で、
Tr2のソース電極４１′との間に、本発明の
UMOS―SITインバータ集積回路の電源電圧Vd
を印加する。４４′はインジエクタTr1のソース
電極で、インジエクタTr1のゲート電極４８と
Tr2のゲート電極４６とを接続する配線層でもあ
る。出力はTr2のドレイン電極４５―１，４５―
２，４５―３のそれぞれの上に接続されたドレイ
ン電極４５′―１，４５′―２，４５′―３から取
り出す。４７，５０は厚い絶縁膜で、特に５０は
Tr2のゲート―ソース間容量を小さくする効果を
有する。５３はTr1のゲート絶縁膜である。 43' is the drain electrode of injector Tr 1 ;
The present invention is connected between the source electrode 41' of Tr 2 and
UMOS-SIT inverter integrated circuit power supply voltage Vd
Apply. 44' is the source electrode of the injector Tr 1 , which is connected to the gate electrode 48 of the injector Tr 1 .
It is also a wiring layer that connects to the gate electrode 46 of Tr 2 . The output is the drain electrode of Tr 2 45-1, 45-
The drain electrodes 45'-1, 45'-2, and 45'-3 are connected to the drain electrodes 45'-1, 45'-2, and 45'-3, respectively. 47 and 50 are thick insulating films, especially 50
This has the effect of reducing the gate-source capacitance of Tr 2 . 53 is a gate insulating film of Tr 1 .

n+領域４４、ｐ領域４２、n+基板４１により
Tr3を構成する。第１のゲート絶縁膜５１を、n+
領域４５側の第２のゲート絶縁膜５２よりやや厚
くして、閾値電圧をやや高めにしておけばよい。
直流的に消費される電流はすべてTr3を通つて流
れるのであるから、Tr2の出力数が増えても、
Tr2とは独立にTr3を設計出来、Tr3のゲート幅
や、ドレイン領域の寸法を選ぶことにより、直流
消費電流は十分小さく出来る。 By the n + region 44, p region 42, and n + substrate 41
Configure Tr 3 . The first gate insulating film 51 is
It may be made slightly thicker than the second gate insulating film 52 on the region 45 side, and the threshold voltage may be made slightly higher.
All the current consumed in direct current flows through Tr 3 , so even if the number of outputs of Tr 2 increases,
Tr 3 can be designed independently of Tr 2 , and by selecting the gate width and drain region dimensions of Tr 3 , the DC current consumption can be made sufficiently small.

このような構造にすると、従来のI2L型インバ
ータではインジエクタTr1の電流がインバータ
Tr2に流れ込みTr2を導通状態に変化させ、Tr1か
らTr2を通る電流通路が生じるのに対し、本発明
ではインジエクタTr1からの電流は全くTr2を流
れない。従つて本発明は全く新規な動作原理に基
づくものであり、少数キヤリアの注入による効果
も無く、しかもTr2に電流が流れないから、より
小さな電流で動作可能である。Tr2に電流が流れ
ない点は多出力を取り出すとき特に有効で、低消
費電力での多出力ICが可能となる。 With this structure, in the conventional I 2 L type inverter, the current of injector Tr 1 is
Whereas current flows into Tr 2 and changes Tr 2 into a conductive state, creating a current path from Tr 1 to Tr 2 , in the present invention no current from injector Tr 1 flows through Tr 2 at all. Therefore, the present invention is based on a completely new operating principle, has no effect due to injection of minority carriers, and since no current flows through Tr 2 , it can operate with a smaller current. The fact that no current flows through Tr 2 is particularly effective when extracting multiple outputs, making it possible to create multiple output ICs with low power consumption.

本発明の構造は、従来公知の結晶成長技術、拡
散技術、イオン注入技術、微細加工技術、エツチ
ング技術等により容易に製造できる。 The structure of the present invention can be easily manufactured using conventionally known crystal growth techniques, diffusion techniques, ion implantation techniques, microfabrication techniques, etching techniques, and the like.

本発明の、電流制御電極がＵ字型に切り込まれ
た領域に設けられたＵ型MOS SIT ICは、浮遊
容量が小さく、緻密に配置することができて、入
力電流が小さいままで出力電流が大きく取れる特
長を有し、耐圧が大きく取れしかも接合ゲート型
と異なり少数キヤリアの注入も無く周波数特性も
良好になり、多出力を取り出すことが可能とな
る。従つて、集積回路としては集積度が向上しフ
アンアウト数が大きく、動作速度が速く、低エネ
ルギーで動作する優れたICとなるなどその工業
的価値は高い。 The U-shaped MOS SIT IC of the present invention, in which the current control electrode is provided in the region cut into a U-shape, has small stray capacitance and can be arranged densely, so that the input current remains small and the output current It has the feature that it can take a large amount of energy, has a large breakdown voltage, and unlike the junction gate type, there is no injection of minority carriers, and the frequency characteristics are good, making it possible to extract multiple outputs. Therefore, as an integrated circuit, it has a high degree of industrial value, as it has an improved degree of integration, a large fan-out number, a high operating speed, and is an excellent IC that operates with low energy.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図ａ，ｂ，ｃは従来のＵ字型半導体装置の
実施例の断面図、第２図は本発明の実施例でａは
等価回路図、ｂは平面図、ｃはAA′線に沿う断面
図である。 Figure 1 a, b, and c are cross-sectional views of an embodiment of a conventional U-shaped semiconductor device, and Figure 2 is an embodiment of the present invention, in which a is an equivalent circuit diagram, b is a plan view, and c is a line AA'. FIG.

Claims (1)

【特許請求の範囲】[Claims] １ 第１導電型高不純物密度の第１の半導体領域
４１、前記第１の半導体領域の上部に形成した第
２導電型の第２の半導体領域４２、前記第２の半
導体領域の上部の一部に形成された第１導電型高
不純物密度の第３ ４３、第４ ４４、および少
なく共２つ以上の第５の半導体領域４５―１，４
５―２，４５―３からなる半導体基板と、前記半
導体基板の表面から前記第４および第５の半導体
領域に接して形成されたＵ字型切り込み領域と、
前記Ｕ字型切り込み領域の底部に形成された厚い
絶縁物層５０と、前記第４の半導体領域に接する
前記Ｕ字型切り込み領域側壁上の第１のゲート絶
縁膜５１と、前記第５の半導体領域に接する前記
Ｕ字型切り込み領域側壁上の前記第１のゲート絶
縁膜より薄い第２のゲート絶縁膜５２と、前記絶
縁物層上でかつ前記第１および第２のいずれのゲ
ート絶縁膜にも接する第１のゲート電極４６と、
前記第３、第４の半導体領域の間の第３のゲート
絶縁膜５３上の第２のゲート電極４８と、前記第
１のゲート電極と前記第２のゲート電極とを接続
する配線層４４′とから形成され、前記第２のゲ
ート電極に入力を印加し、前記第５の半導体領域
から出力を取り出すことを特徴とする半導体集積
回路。1. A first semiconductor region 41 of a first conductivity type with high impurity density, a second semiconductor region 42 of a second conductivity type formed on the upper part of the first semiconductor region, and a part of the upper part of the second semiconductor region. the third 43, fourth 44, and at least two or more fifth semiconductor regions 45-1, 4 of the first conductivity type with high impurity density formed in
5-2 and 45-3; a U-shaped cut region formed from the surface of the semiconductor substrate in contact with the fourth and fifth semiconductor regions;
a thick insulating layer 50 formed at the bottom of the U-shaped cut region; a first gate insulating film 51 on a side wall of the U-shaped cut region in contact with the fourth semiconductor region; a second gate insulating film 52 thinner than the first gate insulating film on the side wall of the U-shaped cut region in contact with the region; a first gate electrode 46 that is also in contact with
A second gate electrode 48 on the third gate insulating film 53 between the third and fourth semiconductor regions, and a wiring layer 44' connecting the first gate electrode and the second gate electrode. What is claimed is: 1. A semiconductor integrated circuit formed of a semiconductor integrated circuit, wherein an input is applied to the second gate electrode and an output is taken out from the fifth semiconductor region.
JP14028578A 1978-11-13 1978-11-13 Semiconductor device Granted JPS5565463A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14028578A JPS5565463A (en) 1978-11-13 1978-11-13 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14028578A JPS5565463A (en) 1978-11-13 1978-11-13 Semiconductor device

Publications (2)

Publication Number Publication Date
JPS5565463A JPS5565463A (en) 1980-05-16
JPS638624B2 true JPS638624B2 (en) 1988-02-23

Family

ID=15265216

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14028578A Granted JPS5565463A (en) 1978-11-13 1978-11-13 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5565463A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3988598A2 (en) 2020-10-22 2022-04-27 FUJIFILM Business Innovation Corp. Liquid composition, metallic luster film, and article

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5034785A (en) * 1986-03-24 1991-07-23 Siliconix Incorporated Planar vertical channel DMOS structure
EP0690513B1 (en) * 1986-11-19 1999-05-06 Research Development Corporation of Japan Step-cut insulated gate static induction transistors and method of manufacturing the same
US4761679A (en) * 1986-12-22 1988-08-02 North American Philips Corporation Complementary silicon-on-insulator lateral insulated gate rectifiers
US5164325A (en) * 1987-10-08 1992-11-17 Siliconix Incorporated Method of making a vertical current flow field effect transistor
US4914058A (en) * 1987-12-29 1990-04-03 Siliconix Incorporated Grooved DMOS process with varying gate dielectric thickness
US4992390A (en) * 1989-07-06 1991-02-12 General Electric Company Trench gate structure with thick bottom oxide
US5242845A (en) * 1990-06-13 1993-09-07 Kabushiki Kaisha Toshiba Method of production of vertical MOS transistor
DE4300806C1 (en) * 1993-01-14 1993-12-23 Siemens Ag Vertical MOS transistor prodn. - with reduced trench spacing, without parasitic bipolar effects
US5405794A (en) * 1994-06-14 1995-04-11 Philips Electronics North America Corporation Method of producing VDMOS device of increased power density
US5770878A (en) * 1996-04-10 1998-06-23 Harris Corporation Trench MOS gate device
US5929476A (en) * 1996-06-21 1999-07-27 Prall; Kirk Semiconductor-on-insulator transistor and memory circuitry employing semiconductor-on-insulator transistors
US6500744B2 (en) 1999-09-02 2002-12-31 Micron Technology, Inc. Methods of forming DRAM assemblies, transistor devices, and openings in substrates
JP4939797B2 (en) * 2005-11-01 2012-05-30 ルネサスエレクトロニクス株式会社 Switching semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3988598A2 (en) 2020-10-22 2022-04-27 FUJIFILM Business Innovation Corp. Liquid composition, metallic luster film, and article

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